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CS495313-CVZ - Cirrus Logic

Description: Audio DSPs 32-Bit Decoder DSP w/Dual DSP Engine

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CS495313-CVZ - Cirrus Logic - PCB symbol
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PCB Footprints
CS495313-CVZ - Cirrus Logic PCB footprint - Quad Flat Packages - Quad Flat Packages - 128-pin LQFP
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CS495313-CVZ - Cirrus Logic - 3D model - Quad Flat Packages - 128-pin LQFP
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CS495313-CVZ Details

  • Manufacturer Part Number:

    CS495313-CVZ

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    QFP

  • Pin Count:

    128

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.60

  • Manufacturer:

    Cirrus Logic

  • YTEOL:

    0

  • Consumer IC Type:

    COLOR SIGNAL DECODER

  • JESD-30 Code:

    R-PQFP-G128

  • Length:

    20 mm

  • Number of Functions:

    1

  • Number of Terminals:

    128

  • Operating Temperature-Max:

    70 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP128,.63X.87,20

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max (Vsup):

    1.89 V

  • Supply Voltage-Min (Vsup):

    1.71 V

  • Surface Mount:

    YES

  • Temperature Grade:

    COMMERCIAL

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Width:

    14 mm

CS495313-CVZ Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VDD first, followed by VDDIO, and then the clock signal. This ensures proper device initialization and prevents latch-up.
  • To configure the CS495313-CVZ for master clock mode, set the MCLK pin as the clock source, and set the MCLKDIV pin to the desired clock frequency. Additionally, set the BCLK pin to the desired bit clock frequency.
  • The maximum allowed capacitance for the analog output filters is 10uF. Exceeding this value may affect the device's performance and stability.
  • To implement a 24-bit audio interface, set the DLEN pin to '1' and use the 24-bit data format. Ensure that the data is aligned to the MSB (most significant bit) and that the data is transmitted in the correct byte order.
  • The recommended layout and routing for the CS495313-CVZ involves keeping the analog and digital signals separate, using a solid ground plane, and minimizing the length of the clock signal traces. Additionally, ensure that the power supply decoupling capacitors are placed close to the device.

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CS495313-CVZ Overview

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