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CS5361-KSZ - Cirrus Logic

Description: Cirrus Logic CS5361-KSZ, 24 bit Serial ADC, Dual Differential Input, 24-Pin SOIC

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CS5361-KSZ - Cirrus Logic PCB footprint - Small Outline Packages - Small Outline Packages - 24L SOIC (300 MIL BODY)
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CS5361-KSZ - Cirrus Logic  - 3D model - Small Outline Packages - 24L SOIC (300 MIL BODY)
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CS5361-KSZ Details

  • Manufacturer Part Number:

    CS5361-KSZ

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    SOIC

  • Package Description:

    300 MIL WIDTH, LEAD FREE, SOIC-24

  • Pin Count:

    24

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Cirrus Logic

  • YTEOL:

    0

  • Analog Input Voltage-Max:

    2 V

  • Converter Type:

    ADC, DELTA-SIGMA

  • JESD-30 Code:

    R-PDSO-G24

  • JESD-609 Code:

    e3

  • Length:

    15.4 mm

  • Moisture Sensitivity Level:

    3

  • Number of Analog In Channels:

    2

  • Number of Bits:

    24

  • Number of Functions:

    1

  • Number of Terminals:

    24

  • Operating Temperature-Max:

    70 °C

  • Operating Temperature-Min:

    -10 °C

  • Output Bit Code:

    2'S COMPLEMENT BINARY

  • Output Format:

    SERIAL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP24,.4

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Sample Rate:

    0.192 MHz

  • Seated Height-Max:

    2.65 mm

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    MATTE TIN

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Width:

    7.5 mm

CS5361-KSZ Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply analog power (AVDD) first, followed by digital power (DVDD), and then bring the reset pin (RST) high.
  • To configure the CS5361-KSZ for master clock mode, set the MCLK pin as the clock source, and set the MCLKDIV pin to select the desired clock frequency. Additionally, set the BCK pin to the desired bit clock frequency.
  • The maximum allowed capacitance for the analog input coupling capacitors is 10uF. Exceeding this value may affect the device's performance and stability.
  • To optimize the CS5361-KSZ for low power consumption, use the power-down modes (e.g., PDN pin), reduce the clock frequency, and minimize the analog input signal amplitude.
  • The recommended layout and routing for the CS5361-KSZ involves separating analog and digital signals, using a solid ground plane, and minimizing signal trace lengths and loops.

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CS5361-KSZ Overview

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