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CY7C1061G30-10ZSXI - Infineon

Description: CYPRESS SEMICONDUCTOR - CY7C1061G30-10ZSXI - SRAM, 16MBIT, 1MX16BIT, 10NS, TSOP-II-54

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CY7C1061G30-10ZSXI Details

  • Manufacturer Part Number:

    CY7C1061G30-10ZSXI

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Taiwan, Thailand

  • ECCN Code:

    3A991.b.2.a

  • HTS Code:

    8542.32.00.41

  • Factory Lead Time:

    8 Weeks

  • Manufacturer:

    Infineon Technologies AG

  • YTEOL:

    8

  • Access Time-Max:

    10 ns

  • JESD-30 Code:

    R-PDSO-G54

  • JESD-609 Code:

    e3

  • Length:

    22.415 mm

  • Memory Density:

    16777216 bit

  • Memory IC Type:

    STANDARD SRAM

  • Memory Width:

    16

  • Moisture Sensitivity Level:

    3

  • Number of Functions:

    1

  • Number of Terminals:

    54

  • Number of Words:

    1048576 words

  • Number of Words Code:

    1000000

  • Operating Mode:

    ASYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    1MX16

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TSOP2

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, THIN PROFILE

  • Packing Method:

    BULK

  • Parallel/Serial:

    PARALLEL

  • Peak Reflow Temperature (Cel):

    260

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    2.2 V

  • Supply Voltage-Nom (Vsup):

    3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 65 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Pure Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    DUAL

  • Width:

    10.16 mm

CY7C1061G30-10ZSXI Frequently Asked Questions (FAQs)

  • The CY7C1061G30-10ZSXI has an operating temperature range of 0°C to 70°C.
  • The device has a power-up sequence that requires VCC to be applied before VCCQ, and a power-down sequence that requires VCCQ to be removed before VCC. Refer to the datasheet for specific timing requirements.
  • The recommended termination scheme for the DDR3 interface is ODT (On-Die Termination) with a 50-ohm resistor on the data lines and a 25-ohm resistor on the clock lines.
  • The self-refresh mode can be implemented by asserting the SREF pin low and ensuring that the device is in a valid power state. Refer to the datasheet for specific timing requirements.
  • The CY7C1061G30-10ZSXI supports a maximum clock frequency of 1066 MHz.

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CY7C1061G30-10ZSXI Overview

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