DF2S12FU,H3F footprint, schematic symbol and 3D model by Toshiba

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PCB Footprints

DF2S12FU,H3F - Toshiba PCB footprint - Other - Other - USC (1-1E1A)-1

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Part Number DF2S12FU,H3F
Manufacturer Toshiba
Pin Count 2
Part Category Diode ESD (Uni-directional)
Package Category Other
Footprint Name Other - USC (1-1E1A)-1
Released Date Jul 29, 2020
Last Modified Date Apr 4, 2025 2:48 PM UTC
Pinout / Pin List Click Here (Member Only)

DF2S12FU,H3F Details

Manufacturer Part Number:
DF2S12FU,H3F
Pbfree Code:
Yes
Rohs Code:
Yes
Part Life Cycle Code:
Active
ECCN Code:
EAR99
HTS Code:
8541.10.00.50
Factory Lead Time:
16 Weeks
Manufacturer:
Toshiba America Electronic Components
Breakdown Voltage-Max:
12.6 V
Breakdown Voltage-Min:
11.4 V
Breakdown Voltage-Nom:
12 V
Configuration:
SINGLE
Diode Element Material:
SILICON
Diode Type:
TRANS VOLTAGE SUPPRESSOR DIODE
JESD-30 Code:
R-PDSO-G2
Number of Elements:
1
Number of Terminals:
2
Operating Temperature-Max:
125 °C
Package Body Material:
PLASTIC/EPOXY
Package Shape:
RECTANGULAR
Package Style:
SMALL OUTLINE
Peak Reflow Temperature (Cel):
NOT SPECIFIED
Polarity:
UNIDIRECTIONAL
Power Dissipation-Max:
0.15 W
Reference Standard:
IEC 61000-4-2
Rep Pk Reverse Voltage-Max:
9 V
Reverse Current-Max:
0.05 µA
Reverse Test Voltage:
9 V
Surface Mount:
YES
Technology:
ZENER
Terminal Form:
GULL WING
Terminal Position:
DUAL
Time@Peak Reflow Temperature-Max (s):
NOT SPECIFIED

DF2S12FU,H3F Frequently Asked Questions (FAQs)

Toshiba recommends a PCB layout with a thermal pad connected to a large copper area on the bottom layer, and multiple vias to dissipate heat efficiently.
Toshiba recommends using a heat sink, ensuring good airflow, and following the recommended operating temperature range (up to 150°C) to ensure reliable operation.
The maximum allowable voltage for the DF2S12FU,H3F is 1.5 times the rated voltage (12V) for a short duration (less than 100ms), but it's recommended to operate within the rated voltage range for reliable operation.
Yes, the DF2S12FU,H3F is suitable for high-frequency switching applications up to 100kHz, but ensure proper PCB layout, decoupling, and snubber circuits to minimize ringing and EMI.
Toshiba recommends using a snubber circuit to minimize the effects of internal parasitic inductance and capacitance, and following the recommended PCB layout guidelines to reduce parasitic effects.

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