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EN5364QI - Intel

Description: Conv DC-DC 2.375V to 6.6V Step Down Single-Out 0.6V 6A 20W 68-Pin QFN EP T/R

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PCB Footprints
EN5364QI - Intel PCB footprint - Other - Other - 68-pin QFN
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3D Models
EN5364QI - Intel  - 3D model - Other - 68-pin QFN
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EN5364QI Details

  • Manufacturer Part Number:

    EN5364QI

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    8 X 11 MM, 1.85 MM HEIGHT, ROHS COMPLIANT, QFN-68

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Analog IC - Other Type:

    SWITCHING REGULATOR

  • Control Mode:

    VOLTAGE-MODE

  • Control Technique:

    PULSE WIDTH MODULATION

  • Input Voltage-Max:

    6.6 V

  • Input Voltage-Min:

    2.375 V

  • Input Voltage-Nom:

    5.5 V

  • JESD-30 Code:

    R-XQCC-N68

  • JESD-609 Code:

    e3

  • Length:

    11 mm

  • Moisture Sensitivity Level:

    3

  • Number of Functions:

    1

  • Number of Terminals:

    68

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Current-Max:

    6 A

  • Package Body Material:

    UNSPECIFIED

  • Package Code:

    QCCN

  • Package Equivalence Code:

    LCC68,.31X.43,20

  • Package Shape:

    RECTANGULAR

  • Package Style:

    CHIP CARRIER

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.9 mm

  • Surface Mount:

    YES

  • Switcher Configuration:

    BUCK

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    NO LEAD

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Width:

    8 mm

EN5364QI Frequently Asked Questions (FAQs)

  • A 4-layer PCB with a dedicated ground plane and thermal vias is recommended for optimal thermal performance. Ensure a minimum of 1 oz copper thickness and a thermal relief pattern around the device.
  • Implement a robust thermal management system, including heat sinks, thermal interfaces, and airflow management. Ensure the device is operated within the specified temperature range (–40°C to 125°C) and consider derating the device for high-temperature applications.
  • Power sequencing: VCCIO, VCC, and VREF should be powered up simultaneously. Voltage ramp-up: VCCIO and VCC should ramp up together, followed by VREF. Ensure a monotonic voltage ramp-up to prevent latch-up.
  • Implement proper PCB layout techniques, such as separating analog and digital circuits, using shielding, and minimizing loop areas. Ensure compliance with relevant EMI and EMC standards (e.g., CISPR 22 and IEC 61000-4-2).
  • Use controlled impedance transmission lines (e.g., 50 ohms) and ensure signal lines are properly terminated. Implement signal routing and layer stacking to minimize crosstalk and reflections. Consider using simulation tools to optimize signal integrity.

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EN5364QI Overview

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