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EP2S90F1020C5N - Intel

Description: FPGA, STRATIX II

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EP2S90F1020C5N - Intel PCB footprint - BGA - BGA - 1020 FBGA
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EP2S90F1020C5N - Intel  - 3D model - BGA - 1020 FBGA
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EP2S90F1020C5N Details

  • Manufacturer Part Number:

    EP2S90F1020C5N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    33 X 33 MM, 1 MM PITCH, FBGA-1020

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    640 MHz

  • Combinatorial Delay of a CLB-Max:

    5.962 ns

  • JESD-30 Code:

    S-PBGA-B1020

  • JESD-609 Code:

    e1

  • Length:

    33 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    36384

  • Number of Inputs:

    758

  • Number of Logic Cells:

    90960

  • Number of Outputs:

    750

  • Number of Terminals:

    1020

  • Operating Temperature-Max:

    85 °C

  • Organization:

    36384 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA1020,32X32,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    245

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS; 90 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    33 mm

EP2S90F1020C5N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the EP2S90F1020C5N is -40°C to 100°C.
  • A reliable POR circuit can be implemented using a voltage supervisor IC, such as the MAX809, which can detect power-on and power-down sequences and generate a reset signal to the FPGA.
  • The recommended PCB layout guidelines for the EP2S90F1020C5N include using a 4-layer PCB with a solid ground plane, placing decoupling capacitors near the FPGA, and using controlled impedance traces for high-speed signals.
  • To optimize timing closure, use the Intel Quartus II software to analyze and optimize the design's timing constraints, and consider using pipelining, retiming, and clock domain crossing techniques.
  • The EP2S90F1020C5N requires a configuration memory interface that can provide a 1x or 4x configuration data width, with a maximum clock frequency of 100 MHz.

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EP2S90F1020C5N Overview

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Part Image EP2S90F1020C5N Altera Corporation

Field Programmable Gate Array, 36384 CLBs, 640MHz, 90960-Cell, CMOS, PBGA1020

Part Image EP2S90F1020C5 Intel Corporation

Field Programmable Gate Array, 36384 CLBs, 640MHz, 90960-Cell, CMOS, PBGA1020