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EPM7064LC68-15 - Intel

Description: Altera EPM7064LC68-15, CPLD MAX 7000 EEPROM 64 Cells, 52 I/O, 4 Labs, ISP, 68-Pin PLCC

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PCB Footprints
EPM7064LC68-15 - Intel PCB footprint - Plastic Leaded Chip Carrier - Plastic Leaded Chip Carrier - 68-Lead PLCC
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EPM7064LC68-15 Details

  • Manufacturer Part Number:

    EPM7064LC68-15

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    PLASTIC, LCC-68

  • HTS Code:

    8542.31.00.55

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Additional Feature:

    CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V

  • Clock Frequency-Max:

    100 MHz

  • In-System Programmable:

    NO

  • JESD-30 Code:

    S-PQCC-J68

  • JESD-609 Code:

    e0

  • JTAG BST:

    NO

  • Length:

    24.2316 mm

  • Moisture Sensitivity Level:

    3

  • Number of I/O Lines:

    52

  • Number of Inputs:

    52

  • Number of Macro Cells:

    64

  • Number of Outputs:

    52

  • Number of Terminals:

    68

  • Operating Temperature-Max:

    70 °C

  • Organization:

    0 DEDICATED INPUTS, 52 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    QCCJ

  • Package Equivalence Code:

    LDCC68,1.0SQ

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    15 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    5.08 mm

  • Supply Voltage-Max:

    5.25 V

  • Supply Voltage-Min:

    4.75 V

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    TIN LEAD

  • Terminal Form:

    J BEND

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    QUAD

  • Width:

    24.2316 mm

EPM7064LC68-15 Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VCCINT first, followed by VCCIO, and then configure the device. This ensures that the internal voltage regulators are powered up correctly.
  • The CCLK should be held low during power-up until the device is fully powered up and the configuration process is complete. This ensures that the device is properly configured and avoids any potential issues.
  • The maximum frequency for the CCLK is 10 MHz. Exceeding this frequency may cause configuration errors or device malfunction.
  • To ensure reliable configuration, use a robust configuration clock source, ensure the configuration data is error-free, and use the recommended configuration protocol (e.g., JTAG or Passive Serial).
  • The recommended operating temperature range is 0°C to 85°C (commercial temperature range). Operating the device outside this range may affect its performance and reliability.

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EPM7064LC68-15 Overview

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