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EPM7128ELC84-7 - Intel

Description: CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 128 Macro 68 IOs

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EPM7128ELC84-7 - Intel PCB footprint - Plastic Leaded Chip Carrier - Plastic Leaded Chip Carrier - 84-Pin Plastic J-Lead Chip Carrier (PLCC)—Wire Bond
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EPM7128ELC84-7 Details

  • Manufacturer Part Number:

    EPM7128ELC84-7

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    PLASTIC, LCC-84

  • HTS Code:

    8542.31.00.55

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Additional Feature:

    128 MACROCELLS; CONFIGURABLE I/O OPERATION (3.3V OR 5V); 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK

  • Clock Frequency-Max:

    166.7 MHz

  • In-System Programmable:

    NO

  • JESD-30 Code:

    S-PQCC-J84

  • JESD-609 Code:

    e0

  • JTAG BST:

    NO

  • Length:

    29.3116 mm

  • Moisture Sensitivity Level:

    3

  • Number of I/O Lines:

    68

  • Number of Inputs:

    68

  • Number of Macro Cells:

    128

  • Number of Outputs:

    68

  • Number of Terminals:

    84

  • Operating Temperature-Max:

    70 °C

  • Organization:

    0 DEDICATED INPUTS, 68 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    QCCJ

  • Package Equivalence Code:

    LDCC84,1.2SQ

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    5.08 mm

  • Supply Voltage-Max:

    5.25 V

  • Supply Voltage-Min:

    4.75 V

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    TIN LEAD

  • Terminal Form:

    J BEND

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    QUAD

  • Width:

    29.3116 mm

EPM7128ELC84-7 Frequently Asked Questions (FAQs)

  • Intel provides a reference design guide for PCB layout and thermal management in the 'EPM7128ELC84-7 FPGA Device Family Pin-Out and Pin Description' document. It recommends a 4-layer PCB with a solid ground plane, and thermal vias under the device to dissipate heat.
  • Intel recommends using synchronous clock domains, and provides guidelines for CDC in the 'EPM7128ELC84-7 FPGA Device Family Clocking and PLL User Guide'. It suggests using synchronizers, FIFOs, or handshake signals to transfer data between clock domains.
  • The commercial temperature range for EPM7128ELC84-7 is 0°C to 85°C, and the industrial temperature range is -40°C to 100°C. However, it's recommended to check the specific temperature range for the desired application and to consult with Intel support for custom temperature requirements.
  • The I/O banks and voltage levels can be configured using the Intel Quartus Prime software. The software provides a GUI-based interface to select the I/O standard, voltage level, and other settings for each bank. The 'EPM7128ELC84-7 FPGA Device Family I/O User Guide' provides more information on I/O bank configuration.
  • The power consumption of EPM7128ELC84-7 depends on the device utilization, clock frequency, and operating conditions. Intel provides a power estimator tool in the Quartus Prime software, which can estimate the power consumption based on the design. The 'EPM7128ELC84-7 FPGA Device Family Power Management User Guide' provides more information on power estimation and management.

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