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EPM7128SLC84-10N - Intel

Description: Altera EPM7128SLC84-10N, CPLD MAX 7000S EEPROM 128 Cells, 68 I/O, 8 Labs, ISP, 84-Pin PLCC

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EPM7128SLC84-10N - Intel PCB footprint - Plastic Leaded Chip Carrier - Plastic Leaded Chip Carrier - 84-Pin Plastic J-Lead Chip Carrier (PLCC)—Wire Bond
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EPM7128SLC84-10N Details

  • Manufacturer Part Number:

    EPM7128SLC84-10N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    PLASTIC, LCC-84

  • HTS Code:

    8542.31.00.55

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Additional Feature:

    CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V

  • Clock Frequency-Max:

    125 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PQCC-J84

  • JESD-609 Code:

    e3

  • JTAG BST:

    YES

  • Length:

    29.3116 mm

  • Moisture Sensitivity Level:

    3

  • Number of I/O Lines:

    68

  • Number of Inputs:

    68

  • Number of Macro Cells:

    128

  • Number of Outputs:

    68

  • Number of Terminals:

    84

  • Operating Temperature-Max:

    70 °C

  • Organization:

    0 DEDICATED INPUTS, 68 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    QCCJ

  • Package Equivalence Code:

    LDCC84,1.2SQ

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    10 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    5.08 mm

  • Supply Voltage-Max:

    5.25 V

  • Supply Voltage-Min:

    4.75 V

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    MATTE TIN

  • Terminal Form:

    J BEND

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    QUAD

  • Width:

    29.3116 mm

EPM7128SLC84-10N Frequently Asked Questions (FAQs)

  • The recommended operating temperature range for the EPM7128SLC84-10N is 0°C to 85°C (commercial temperature range) or -40°C to 100°C (industrial temperature range), depending on the specific application and requirements.
  • A reliable POR circuit can be implemented using a voltage supervisor IC, such as the MAX809, which can detect power-on and power-down conditions and generate a reset signal to the EPM7128SLC84-10N. The voltage supervisor IC should be connected to the VCC pin of the EPM7128SLC84-10N.
  • The maximum clock frequency supported by the EPM7128SLC84-10N is 100 MHz. However, the actual clock frequency may be limited by the specific application and the clock signal quality.
  • To optimize the EPM7128SLC84-10N for low power consumption, use the following techniques: 1) use the lowest possible clock frequency, 2) minimize the number of active resources, 3) use the power-down mode when the device is not in use, and 4) optimize the design to reduce switching activity.
  • The maximum current rating for the EPM7128SLC84-10N is 100 mA per pin, with a total current limit of 500 mA for the entire device.

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EPM7128SLC84-10N Overview

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Part Image EPM7128SLC84-10N Altera Corporation

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Part Image EPM7128SLC84-10 Altera Corporation

EE PLD, 10ns, 128-Cell, CMOS, PQCC84