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G3R160MT12J - GeneSiC Semiconductor

Description: MOSFET 1200V 160mO TO-263-7 G3R SiC MOSFET

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G3R160MT12J - GeneSiC Semiconductor PCB footprint - Other - Other - G3R160MT12J-2
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G3R160MT12J Details

  • Manufacturer Part Number:

    G3R160MT12J

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Country Of Origin:

    USA

  • ECCN Code:

    EAR99

  • Manufacturer:

    GeneSic Semiconductor Inc

  • Avalanche Energy Rating (Eas):

    93 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE AND KELVIN SENSOR

  • DS Breakdown Voltage-Min:

    1200 V

  • Drain Current-Max (ID):

    19 A

  • Drain-source On Resistance-Max:

    0.18 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    1.8 pF

  • JEDEC-95 Code:

    TO-263

  • JESD-30 Code:

    R-PSSO-G7

  • Number of Elements:

    1

  • Number of Terminals:

    7

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    110 W

  • Pulsed Drain Current-Max (IDM):

    35 A

  • Reference Standard:

    IEC-60747-8-4

  • Surface Mount:

    YES

  • Terminal Form:

    GULL WING

  • Terminal Position:

    SINGLE

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON CARBIDE

G3R160MT12J Frequently Asked Questions (FAQs)

  • A 2-layer or 4-layer PCB with a thermal relief pattern and a large copper area for heat dissipation is recommended. The datasheet provides a recommended PCB layout, but it's essential to consult with a thermal expert or perform thermal simulations to ensure optimal performance.
  • To ensure proper biasing, follow the recommended biasing circuit in the datasheet, and ensure the gate driver is capable of providing the required voltage and current. Additionally, consider using a gate resistor to slow down the switching transition and reduce ringing.
  • Monitor the device's junction temperature, drain-source voltage, and gate-source voltage to prevent device failure. Also, ensure the device is operated within the recommended safe operating area (SOA) to prevent thermal runaway and electrical overstress.
  • Use proper PCB layout techniques, such as separating the high-frequency and low-frequency circuits, and use shielding or filtering to minimize EMI. Additionally, consider using a common-mode choke or a ferrite bead to reduce high-frequency noise.
  • Perform thorough testing and validation procedures, including electrical characterization, thermal testing, and reliability testing. Consult the datasheet and relevant industry standards (e.g., JEDEC) for guidance on testing and validation procedures.

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