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GD05MPS17H - GeneSiC Semiconductor

Description: Schottky Diodes & Rectifiers 1700V 5A TO-247-2 SiC Schottky MPS

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PCB Footprints
GD05MPS17H - GeneSiC Semiconductor PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - TO-247-2.1
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3D Models
GD05MPS17H - GeneSiC Semiconductor  - 3D model - Transistor Outline, Vertical - TO-247-2.1
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GD05MPS17H Details

  • Manufacturer Part Number:

    GD05MPS17H

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Country Of Origin:

    USA

  • ECCN Code:

    EAR99

  • HTS Code:

    8541.10.00.80

  • Manufacturer:

    GeneSic Semiconductor Inc

  • YTEOL:

    6

  • Additional Feature:

    FREE WHEELING DIODE, PD-CASE

  • Application:

    EFFICIENCY

  • Case Connection:

    CATHODE

  • Configuration:

    SINGLE

  • Diode Element Material:

    SILICON CARBIDE

  • Diode Type:

    RECTIFIER DIODE

  • Forward Voltage-Max (VF):

    1.8 V

  • JEDEC-95 Code:

    TO-247

  • JESD-30 Code:

    R-PSFM-T2

  • Non-rep Pk Forward Current-Max:

    50 A

  • Number of Elements:

    1

  • Number of Phases:

    1

  • Number of Terminals:

    2

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Output Current-Max:

    15 A

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLANGE MOUNT

  • Power Dissipation-Max:

    141 W

  • Rep Pk Reverse Voltage-Max:

    1700 V

  • Reverse Current-Max:

    20 µA

  • Reverse Test Voltage:

    1700 V

  • Surface Mount:

    NO

  • Technology:

    SCHOTTKY

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    SINGLE

GD05MPS17H Frequently Asked Questions (FAQs)

  • GeneSic recommends a 2-layer or 4-layer PCB with a thermal pad connected to a large copper area for heat dissipation. A minimum of 1 oz copper thickness is recommended. Additionally, a thermal interface material (TIM) with a thermal conductivity of 1 W/m-K or higher is suggested.
  • The GD05MPS17H requires a specific biasing scheme to achieve optimal performance. GeneSic recommends following the application note AN-1101 for proper biasing and configuration. Additionally, the device should be operated within the recommended operating conditions and derating guidelines.
  • GeneSic recommends following standard ESD protection procedures, such as using an ESD wrist strap or mat, and handling the device by the body or leads only. The device should be stored in an anti-static bag or tube when not in use. Additionally, the device should be soldered using a low-temperature soldering iron (< 250°C) and a solder with a melting point above 217°C.
  • GeneSic recommends following the troubleshooting guide in the application note AN-1102 for common issues. Additionally, the device's built-in protection features, such as over-temperature shutdown and UVLO, can be used to identify and diagnose faults. A thorough understanding of the device's operating conditions and application circuit is also essential for effective troubleshooting.
  • The GD05MPS17H has undergone rigorous reliability and qualification tests, including HTRB (High-Temperature Reverse Bias), HTGB (High-Temperature Gate Bias), and Latch-Up tests. The device is also qualified according to AEC-Q101 and meets the requirements of ISO/TS 16949. GeneSic provides a detailed reliability report and qualification data upon request.

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