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GD10MPS12A - GeneSiC Semiconductor

Description: GD10MPS12A

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GD10MPS12A - GeneSiC Semiconductor - PCB symbol
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PCB Footprints
GD10MPS12A - GeneSiC Semiconductor PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - TO-220-2
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3D Models
GD10MPS12A - GeneSiC Semiconductor - 3D model - Transistor Outline, Vertical - TO-220-2
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GD10MPS12A Details

  • Manufacturer Part Number:

    GD10MPS12A

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    TO-220, 2 PIN

  • Country Of Origin:

    USA

  • ECCN Code:

    EAR99

  • HTS Code:

    8541.10.00.80

  • Manufacturer:

    GeneSic Semiconductor Inc

  • YTEOL:

    6

  • Additional Feature:

    FREE WHEELING DIODE, PD-CASE

  • Application:

    EFFICIENCY

  • Case Connection:

    CATHODE

  • Configuration:

    SINGLE

  • Diode Element Material:

    SILICON CARBIDE

  • Diode Type:

    RECTIFIER DIODE

  • Forward Voltage-Max (VF):

    1.8 V

  • JEDEC-95 Code:

    TO-220AC

  • JESD-30 Code:

    R-PSFM-T2

  • Non-rep Pk Forward Current-Max:

    80 A

  • Number of Elements:

    1

  • Number of Phases:

    1

  • Number of Terminals:

    2

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Output Current-Max:

    24 A

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLANGE MOUNT

  • Power Dissipation-Max:

    163 W

  • Rep Pk Reverse Voltage-Max:

    1200 V

  • Reverse Current-Max:

    10 µA

  • Reverse Test Voltage:

    1200 V

  • Surface Mount:

    NO

  • Technology:

    SCHOTTKY

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    SINGLE

GD10MPS12A Frequently Asked Questions (FAQs)

  • A 2-layer or 4-layer PCB with a thermal relief pattern and a solid ground plane is recommended. Ensure a minimum of 1 oz copper thickness and a thermal via array under the device.
  • Implement a robust thermal management system, including a heat sink, thermal interface material, and a cooling fan. Monitor junction temperature (TJ) and adjust the system design accordingly.
  • A gate driver with a high current capability (>1A) and a low output impedance (<10 ohms) is recommended. Consider using a dedicated gate driver IC or a discrete circuit with a low-inductance layout.
  • Use a shielded enclosure, keep high-frequency traces short, and use a common-mode choke or ferrite bead to filter out high-frequency noise. Ensure proper grounding and decoupling of the device.
  • The high dv/dt rating requires careful consideration of layout parasitics, PCB trace impedance, and EMI filtering. Ensure a low-inductance layout and consider adding a snubber circuit to reduce voltage spikes.

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GD10MPS12A Overview

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