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HSMG-C280 - Avago Technologies

Description: Groen 572nm Led-indicatie - Discreet 2,2V 0402 (1005 metrisch)

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PCB Footprints
HSMG-C280 - Avago Technologies PCB footprint - Other - Other - HSMG-C280-10
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3D Models
HSMG-C280 - Avago Technologies  - 3D model - Other - HSMG-C280-10
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HSMG-C280 Details

  • Manufacturer Part Number:

    HSMG-C280

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    1 X 0.50 MM, 0.40 MM HEIGHT, PLASTIC, MINIATURE, SMT, 2 PIN

  • Reach Compliance Code:

    Compliant

  • ECCN Code:

    EAR99

  • HTS Code:

    8541.40.20.00

  • Manufacturer:

    Avago Technologies

  • YTEOL:

    7

  • Color:

    GREEN

  • Color@Wavelength:

    Green

  • Configuration:

    SINGLE

  • Forward Current-Max:

    0.02 A

  • Forward Voltage-Max:

    2.6 V

  • JESD-609 Code:

    e4

  • Lens Type:

    UNTINTED DIFFUSED

  • Luminous Intensity-Nom:

    15.0 mcd

  • Mounting Feature:

    SURFACE MOUNT

  • Number of Functions:

    1

  • Number of Terminals:

    2

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -30 °C

  • Optoelectronic Device Type:

    SINGLE COLOR LED

  • Overall Height:

    0.4 mm

  • Packing Method:

    TR, 7 INCH

  • Peak Wavelength:

    570 nm

  • Reverse Voltage-Max:

    5 V

  • Shape:

    RECTANGULAR

  • Size:

    1 mm

  • Surface Mount:

    YES

  • Terminal Finish:

    Gold (Au) - with Nickel (Ni) barrier

  • Terminal Pitch:

    1 mm

  • Viewing Angle:

    130 deg

HSMG-C280 Frequently Asked Questions (FAQs)

  • Broadcom recommends a 4-layer PCB with a solid ground plane, and thermal vias under the device to dissipate heat. A thermal pad on the bottom of the package should be connected to a heat sink or a thermal interface material.
  • Use a low-noise, high-PSRR power supply with a minimum of 1A current capability. Decouple the power pins with 10uF and 100nF capacitors, and add a 10uF capacitor on the AVDD pin.
  • Use a single 25MHz clock source for the device, and use the internal PLL to generate the required clock frequencies. Ensure the clock signal has a low jitter and is properly terminated.
  • Assert the reset pin (RST_N) low for at least 10ms during power-up, and then release it to allow the device to boot. Ensure the boot sequence is correct, and the device is properly configured before releasing the reset.
  • Use a controlled impedance PCB design, and ensure the signal integrity by using differential pairs, and adding series termination resistors. Also, use a common clock and data alignment for the high-speed interfaces.

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HSMG-C280 Overview

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