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ICE40LP1K-CB121 - Lattice Semiconductor

Description: ICE40LP1K-CB121, FPGA iCE40 LP 1280 Cells, 64kbit, 160 Blocks, 1.14 → 1.26 V 121-Pin CSBGA

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PCB Footprints
ICE40LP1K-CB121 - Lattice Semiconductor PCB footprint - BGA - BGA - 121-Ball csBGA
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3D Models
ICE40LP1K-CB121 - Lattice Semiconductor  - 3D model - BGA - 121-Ball csBGA
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ICE40LP1K-CB121 Details

  • Manufacturer Part Number:

    ICE40LP1K-CB121

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    8

  • Clock Frequency-Max:

    133 MHz

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B121

  • JESD-609 Code:

    e1

  • Length:

    6 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    160

  • Number of Inputs:

    92

  • Number of Logic Cells:

    1280

  • Number of Outputs:

    92

  • Number of Terminals:

    121

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    160 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA121,11X11,20

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    BOTTOM

  • Width:

    6 mm

ICE40LP1K-CB121 Frequently Asked Questions (FAQs)

  • Lattice provides a PCB Design and Layout Guide for the ICE40LP1K-CB121, which recommends a 4-layer PCB stackup, specific routing guidelines for clock signals, and decoupling capacitor placement. It's essential to follow these guidelines to ensure signal integrity and minimize noise.
  • The ICE40LP1K-CB121 has a built-in POR circuit, but it's recommended to use an external POR circuit to ensure a clean and reliable power-on reset. A simple POR circuit can be implemented using a voltage supervisor IC, such as the TLV7031, and a few external components.
  • The built-in SPI flash memory interface on the ICE40LP1K-CB121 has limitations on the maximum clock frequency, data transfer size, and supported flash memory devices. It's essential to check the datasheet and application notes for specific guidelines and recommendations to ensure reliable operation.
  • To optimize power consumption and reduce heat generation, it's recommended to use the ICE40LP1K-CB121's built-in power management features, such as dynamic voltage and frequency scaling, and clock gating. Additionally, optimizing the design's clock frequency, using low-power modes, and minimizing unnecessary logic can also help reduce power consumption.
  • To implement a reliable and efficient JTAG interface, it's recommended to use a dedicated JTAG connector, follow the recommended signal routing and termination guidelines, and use a high-quality JTAG cable. Additionally, using a JTAG interface with a built-in voltage regulator and level shifter can help ensure reliable operation.

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ICE40LP1K-CB121 Overview

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