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ICE40LP384-CM36TR - Lattice Semiconductor

Description: FPGA iCE40 LP Family 384 Cells 40nm Technology 1.2V 36-Pin UCBGA T/R

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ICE40LP384-CM36TR - Lattice Semiconductor PCB footprint - BGA - BGA - 36-Ball ucBGA Package Option 1
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3D Models
ICE40LP384-CM36TR - Lattice Semiconductor  - 3D model - BGA - 36-Ball ucBGA Package Option 1
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ICE40LP384-CM36TR Details

  • Manufacturer Part Number:

    ICE40LP384-CM36TR

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    8

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B36

  • JESD-609 Code:

    e1

  • Length:

    2.5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    48

  • Number of Inputs:

    25

  • Number of Logic Cells:

    384

  • Number of Outputs:

    25

  • Number of Terminals:

    36

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    48 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA36,6X6,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Width:

    2.5 mm

ICE40LP384-CM36TR Frequently Asked Questions (FAQs)

  • Lattice provides a PCB design guide and layout recommendations in their documentation, including guidelines for signal integrity, power distribution, and thermal management. It's essential to follow these guidelines to ensure reliable operation and minimize signal degradation.
  • To optimize power consumption, use the Lattice Power Calculator tool to estimate power consumption based on your design requirements. Implement power-saving techniques such as clock gating, voltage scaling, and dynamic voltage and frequency scaling. Additionally, use the FPGA's built-in power management features, such as the Power Manager IP core.
  • The ICE40LP384-CM36TR is rated for commercial temperature range (-40°C to 85°C) and industrial temperature range (-40°C to 100°C) options. Ensure that your design operates within the specified temperature range and follows the recommended operating conditions, including voltage, current, and humidity limits.
  • Use the Lattice Diamond software to generate a reliable configuration bitstream. Implement a robust configuration and programming strategy, including error detection and correction mechanisms. Ensure that the FPGA is properly powered and clocked during configuration, and follow the recommended programming protocols.
  • Lattice provides a range of development tools, including the Lattice Diamond software, Lattice Radiant software, and the ICEcube2 development environment. Additionally, there are various third-party tools and resources available, including IP cores, reference designs, and community forums.

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ICE40LP384-CM36TR Overview

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Part Image ICE40LP384-CM36 Lattice Semiconductor Corporation

Field Programmable Gate Array, 48 CLBS, 384-Cell, CMOS, PBGA36