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ICE40LP384-SG32TR - Lattice Semiconductor

Description: FPGA iCE40 LP Family 384 Cells 40nm Technology 1.2V 32-Pin QFN EP T/R

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PCB Footprints
ICE40LP384-SG32TR - Lattice Semiconductor PCB footprint - Quad Flat No-Lead - Quad Flat No-Lead - 32-Pin QFN
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3D Models
ICE40LP384-SG32TR - Lattice Semiconductor  - 3D model - Quad Flat No-Lead - 32-Pin QFN
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ICE40LP384-SG32TR Details

  • Manufacturer Part Number:

    ICE40LP384-SG32TR

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    8

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-XQCC-N32

  • JESD-609 Code:

    e3

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    48

  • Number of Inputs:

    21

  • Number of Logic Cells:

    384

  • Number of Outputs:

    21

  • Number of Terminals:

    32

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    48 CLBS

  • Package Body Material:

    UNSPECIFIED

  • Package Code:

    HVQCCN

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    NO LEAD

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Width:

    5 mm

ICE40LP384-SG32TR Frequently Asked Questions (FAQs)

  • The ICE40LP384-SG32TR has an operating temperature range of -40°C to 100°C.
  • Lattice recommends using a synchronizer or a FIFO to implement CDC in the ICE40LP384-SG32TR. The iCE40 LP/HX/LM FPGA Fabric User Guide provides more information on CDC implementation.
  • The power consumption of the ICE40LP384-SG32TR depends on the specific design and operating conditions. However, the typical power consumption is around 100-200 mW at 1.2V and 25°C.
  • No, the ICE40LP384-SG32TR is not suitable for high-speed interfaces like PCIe or SATA due to its limited transceiver bandwidth and lack of high-speed serial interfaces.
  • The ICE40LP384-SG32TR can be programmed using the Lattice iCEcube2 software and a programming cable like the iCEstick or the HW-USBN-2A.

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ICE40LP384-SG32TR Overview

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