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ICE5LP1K-SWG36ITR50 - Lattice Semiconductor

Description: FPGA iCE40 Ultra Family 1100 Cells 40nm Technology 1.2V 36-Pin WLCSP T/R

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PCB Footprints
ICE5LP1K-SWG36ITR50 - Lattice Semiconductor PCB footprint - BGA - BGA - 36-Ball WLCS Package Option 1: iCE40 Ultra
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3D Models
ICE5LP1K-SWG36ITR50 - Lattice Semiconductor  - 3D model - BGA - 36-Ball WLCS Package Option 1: iCE40 Ultra
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ICE5LP1K-SWG36ITR50 Details

  • Manufacturer Part Number:

    ICE5LP1K-SWG36ITR50

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    0

  • Combinatorial Delay of a CLB-Max:

    9 ns

  • JESD-30 Code:

    S-PBGA-B36

  • Length:

    2.078 mm

  • Moisture Sensitivity Level:

    1

  • Number of CLBs:

    138

  • Number of Inputs:

    26

  • Number of Logic Cells:

    1100

  • Number of Outputs:

    26

  • Number of Terminals:

    36

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    138 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA36,6X6,14

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Packing Method:

    TR

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    0.491 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.35 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    2.078 mm

ICE5LP1K-SWG36ITR50 Frequently Asked Questions (FAQs)

  • The power consumption of the ICE5LP1K-SWG36ITR50 depends on the operating frequency, voltage, and usage. However, according to the datasheet, the typical static power consumption is around 50-70 mW, and the dynamic power consumption can range from 100-500 mW depending on the usage.
  • The ICE5LP1K-SWG36ITR50 can be programmed using Lattice's iCEcube2 software, which provides a comprehensive development environment for designing, implementing, and testing FPGA-based systems. The device can also be programmed using a programming cable and a third-party programmer.
  • The maximum operating frequency of the ICE5LP1K-SWG36ITR50 is around 200-250 MHz, depending on the specific implementation and usage. However, the actual operating frequency may be limited by the system clock, PLL settings, and other factors.
  • The ICE5LP1K-SWG36ITR50 is not suitable for high-speed interfaces like PCIe or SATA due to its limited bandwidth and speed. It is primarily designed for low-power, low-speed applications such as IoT, wearables, and other battery-powered devices.
  • The ICE5LP1K-SWG36ITR50 has built-in security features such as secure boot, encryption, and access control. These features can be implemented using Lattice's security IP cores and software tools. Additionally, users can implement their own custom security solutions using the FPGA's programmable logic.

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ICE5LP1K-SWG36ITR50 Overview

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