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IDW40G120C5BFKSA1 - Infineon

Description: Schottky Diodes & Rectifiers SIC CHIP/DISCRETE

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Symbol
IDW40G120C5BFKSA1 - Infineon - PCB symbol
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PCB Footprints
IDW40G120C5BFKSA1 - Infineon PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - PG-TO247-3_2020
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3D Models
IDW40G120C5BFKSA1 - Infineon - 3D model - Transistor Outline, Vertical - PG-TO247-3_2020
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IDW40G120C5BFKSA1 Details

  • Manufacturer Part Number:

    IDW40G120C5BFKSA1

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Austria, Mainland China

  • ECCN Code:

    EAR99

  • HTS Code:

    8541.10.00.80

  • Manufacturer:

    Infineon Technologies AG

  • YTEOL:

    5

  • Additional Feature:

    HIGH RELIABILITY, PD-CASE

  • Application:

    EFFICIENCY

  • Breakdown Voltage-Min:

    1200 V

  • Case Connection:

    CATHODE

  • Configuration:

    COMMON CATHODE, 2 ELEMENTS

  • Diode Element Material:

    SILICON CARBIDE

  • Diode Type:

    RECTIFIER DIODE

  • Forward Voltage-Max (VF):

    1.65 V

  • JEDEC-95 Code:

    TO-247

  • JESD-30 Code:

    R-PSFM-T3

  • JESD-609 Code:

    e3

  • Non-rep Pk Forward Current-Max:

    145 A

  • Number of Elements:

    2

  • Number of Phases:

    1

  • Number of Terminals:

    3

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Output Current-Max:

    55 A

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    FLANGE MOUNT

  • Power Dissipation-Max:

    402 W

  • Rep Pk Reverse Voltage-Max:

    1200 V

  • Reverse Current-Max:

    166 µA

  • Reverse Test Voltage:

    1200 V

  • Surface Mount:

    NO

  • Technology:

    SCHOTTKY

  • Terminal Finish:

    Tin (Sn)

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    SINGLE

IDW40G120C5BFKSA1 Frequently Asked Questions (FAQs)

  • A 2-layer or 4-layer PCB with a thermal via array underneath the device is recommended. The thermal vias should be connected to a solid copper plane on the bottom layer to dissipate heat efficiently.
  • Ensure proper heat sinking, use a thermal interface material (TIM) with a thermal conductivity of at least 1 W/mK, and follow the recommended PCB layout guidelines. Also, consider using a heat sink with a thermal resistance of less than 10°C/W.
  • The maximum allowed voltage transient on the input pins is ±500 mV, with a duration of less than 100 ns. Exceeding this may cause damage to the device.
  • Use a shielded enclosure, keep the device away from high-frequency sources, and use a common-mode choke or ferrite bead on the input lines. Also, ensure good PCB layout practices, such as separating analog and digital grounds.
  • A 10 nF to 100 nF ceramic capacitor is recommended for input decoupling, depending on the specific application requirements. A larger capacitance value may be needed for high-ripple or high-current applications.

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IDW40G120C5BFKSA1 Overview

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