Power Integrations provides a recommended PCB layout in their application note AN-63, which includes guidelines for thermal vias, copper pours, and component placement to minimize thermal resistance and ensure reliable operation.
The output capacitor selection depends on the output voltage, output current, and ripple requirements. Power Integrations recommends using a low-ESR capacitor with a capacitance value between 10uF to 22uF, and a voltage rating of at least 1.5 times the output voltage. Additionally, the capacitor should be placed close to the IC to minimize parasitic inductance.
The maximum junction temperature (Tj) for the INN3670C-H605-TL is 150°C. However, it's recommended to design for a maximum Tj of 125°C to ensure reliable operation and minimize derating. This can be achieved by providing adequate heat sinking, using a thermal interface material, and optimizing the PCB layout for thermal performance.
To ensure EMC, follow the guidelines in Power Integrations' application note AN-64, which includes recommendations for layout, component selection, and shielding. Additionally, use a common-mode choke and Y-capacitors to filter the input and output, and consider using a metal shield or enclosure to contain electromagnetic radiation.
Power Integrations recommends using a ceramic or film capacitor with a value between 1uF to 10uF, and a voltage rating of at least 1.5 times the input voltage. The capacitor should be placed close to the IC's input pins to minimize parasitic inductance and ensure stable operation.
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