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J112G - onsemi

Description: JFET N-Channel 35 V 350 mW Through Hole TO-92 (TO-226) , 50 Ohms , -65°C ~ 150°C (TJ)

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PCB Footprints
J112G - onsemi PCB footprint - Other - Other - TO−92 (TO−226) CASE 29−11 ISSUE AM_2026-1.1
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3D Models
J112G - onsemi  - 3D model - Other - TO−92 (TO−226) CASE 29−11 ISSUE AM_2026-1.1
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J112G Details

  • Manufacturer Part Number:

    J112G

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TO-92 (TO-226) 5.33mm Body Height

  • Pin Count:

    3

  • Manufacturer Package Code:

    29-11

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    4 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    0

  • Configuration:

    SINGLE

  • Drain-source On Resistance-Max:

    50 Ω

  • FET Technology:

    JUNCTION

  • Feedback Cap-Max (Crss):

    5 pF

  • JEDEC-95 Code:

    TO-92

  • JESD-30 Code:

    O-PBCY-T3

  • JESD-609 Code:

    e1

  • Number of Elements:

    1

  • Number of Terminals:

    3

  • Operating Mode:

    DEPLETION MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    ROUND

  • Package Style:

    CYLINDRICAL

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    0.4 W

  • Qualification Status:

    Not Qualified

  • Surface Mount:

    NO

  • Terminal Finish:

    TIN SILVER COPPER

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    BOTTOM

  • Transistor Application:

    CHOPPER

  • Transistor Element Material:

    SILICON

J112G Frequently Asked Questions (FAQs)

  • The J112G can operate from -55°C to 150°C, but the recommended operating temperature range is -40°C to 125°C for optimal performance.
  • To ensure proper biasing, the J112G requires a minimum of 10mA of quiescent current (IQ) and a supply voltage (VCC) between 3.5V and 5.5V. Additionally, the input voltage (VIN) should be within 1.5V to 5.5V.
  • To minimize noise and ensure reliability, it is recommended to use a 4-layer PCB with a solid ground plane, keep the input and output traces separate, and use a decoupling capacitor (e.g., 100nF) between VCC and GND.
  • The J112G has built-in ESD protection, but it's still recommended to follow proper ESD handling procedures during assembly and testing. Use an ESD wrist strap or mat, and ensure that the PCB is properly grounded.
  • Store the J112G in a dry, cool place, away from direct sunlight and moisture. Handle the device by the body, avoiding touching the leads or die. Use anti-static packaging and follow proper ESD handling procedures.

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J112G Overview

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