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LC4064ZE-7TN100I - Lattice Semiconductor

Description: CPLD - Complex Programmable Logic Devices 64MC 64 I/O Ultra Low Power 1.8V

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LC4064ZE-7TN100I - Lattice Semiconductor PCB footprint - Quad Flat Packages - Quad Flat Packages - TN100
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LC4064ZE-7TN100I - Lattice Semiconductor  - 3D model - Quad Flat Packages - TN100
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LC4064ZE-7TN100I Details

  • Manufacturer Part Number:

    LC4064ZE-7TN100I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    QFP

  • Package Description:

    14 X 14 MM, LEAD FREE, TQFP-100

  • Pin Count:

    100

  • Country Of Origin:

    Indonesia, Japan, Malaysia, Philippines, Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    5

  • Additional Feature:

    YES

  • Clock Frequency-Max:

    111 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PQFP-G100

  • JESD-609 Code:

    e3

  • JTAG BST:

    YES

  • Length:

    14 mm

  • Moisture Sensitivity Level:

    3

  • Number of Dedicated Inputs:

    10

  • Number of I/O Lines:

    64

  • Number of Inputs:

    74

  • Number of Macro Cells:

    64

  • Number of Outputs:

    64

  • Number of Terminals:

    100

  • Operating Temperature-Max:

    105 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    10 DEDICATED INPUTS, 64 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP100,.63SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max:

    1.9 V

  • Supply Voltage-Min:

    1.7 V

  • Supply Voltage-Nom:

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Width:

    14 mm

LC4064ZE-7TN100I Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VCCIO before VCC. This ensures that the I/O banks are powered up after the core voltage is stable.
  • To implement a CDC, use a synchronizer circuit or a FIFO-based CDC. The synchronizer circuit can be implemented using a double-flop synchronizer or a pulse synchronizer. The FIFO-based CDC uses a FIFO to transfer data between clock domains.
  • The maximum frequency of operation for the LC4064ZE-7TN100I is 150 MHz. However, this frequency may vary depending on the specific application and the complexity of the design.
  • To optimize power consumption, use the power management features of the device, such as the power-down mode and the clock gating feature. Additionally, optimize the clock frequency and voltage to minimize power consumption.
  • The maximum current rating for the LC4064ZE-7TN100I is 100 mA per I/O bank. However, this current rating may vary depending on the specific application and the operating conditions.

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