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LC4128ZE-7MN144C - Lattice Semiconductor

Description: LATTICE SEMICONDUCTOR - LC4128ZE-7MN144C - CPLD, 128, 96 I/O's, BGA, 144 Pins, 200 MHz

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LC4128ZE-7MN144C - Lattice Semiconductor PCB footprint - BGA - BGA - 144-Ball csBGA
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LC4128ZE-7MN144C - Lattice Semiconductor  - 3D model - BGA - 144-Ball csBGA
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LC4128ZE-7MN144C Details

  • Manufacturer Part Number:

    LC4128ZE-7MN144C

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    BGA

  • Package Description:

    7 X 7 MM, 0.5 MM PITCH, LEAD FREE, CSBGA-144

  • Pin Count:

    144

  • Country Of Origin:

    Japan, Malaysia, Philippines, Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    5

  • Additional Feature:

    YES

  • Clock Frequency-Max:

    111 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PBGA-B144

  • JESD-609 Code:

    e1

  • JTAG BST:

    YES

  • Length:

    7 mm

  • Moisture Sensitivity Level:

    3

  • Number of Dedicated Inputs:

    4

  • Number of I/O Lines:

    96

  • Number of Inputs:

    100

  • Number of Macro Cells:

    128

  • Number of Outputs:

    96

  • Number of Terminals:

    144

  • Operating Temperature-Max:

    90 °C

  • Organization:

    4 DEDICATED INPUTS, 96 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TFBGA

  • Package Equivalence Code:

    BGA144,12X12,20

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.1 mm

  • Supply Voltage-Max:

    1.9 V

  • Supply Voltage-Min:

    1.7 V

  • Supply Voltage-Nom:

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Width:

    7 mm

LC4128ZE-7MN144C Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VCCIO first, followed by VCCINT, and then VREF. This ensures proper device operation and prevents latch-up.
  • To implement a reliable JTAG chain, ensure that each device has a unique TDI/TDO connection, and use a JTAG cable with a 1-kΩ resistor in series with the TCK signal to prevent signal reflection.
  • The maximum frequency for the PLL is 400 MHz, but it can be overclocked up to 450 MHz with reduced margins. However, this is not recommended for production designs.
  • The LC4128ZE-7MN144C is not radiation-hardened and is not suitable for use in radiation-intensive environments. For such applications, consider using radiation-hardened devices or implementing radiation mitigation techniques.
  • To optimize power consumption, use the device's power-saving features, such as clock gating and dynamic voltage frequency scaling. Additionally, optimize your design to minimize switching activity and use low-power modes when possible.

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LC4128ZE-7MN144C Overview

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Part Image LC4128ZE-7MCN144C Lattice Semiconductor Corporation

EE PLD, 7.5ns, 128-Cell, CMOS, PBGA144