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LCMXO2-1200ZE-1SG32C - Lattice Semiconductor

Description: MachXO2 Field Programmable Gate Array (FPGA) IC 32-UFQFN Exposed Pad

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LCMXO2-1200ZE-1SG32C - Lattice Semiconductor PCB footprint - Quad Flat No-Lead - Quad Flat No-Lead - QFN32-XO2 SG32C
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3D Models
LCMXO2-1200ZE-1SG32C - Lattice Semiconductor  - 3D model - Quad Flat No-Lead - QFN32-XO2 SG32C
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LCMXO2-1200ZE-1SG32C Details

  • Manufacturer Part Number:

    LCMXO2-1200ZE-1SG32C

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Date Of Intro:

    2016-03-11

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    19

  • Clock Frequency-Max:

    87 MHz

  • JESD-30 Code:

    S-XQCC-N32

  • JESD-609 Code:

    e3

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    160

  • Number of Inputs:

    21

  • Number of Logic Cells:

    1280

  • Number of Outputs:

    21

  • Number of Terminals:

    32

  • Operating Temperature-Max:

    85 °C

  • Organization:

    160 CLBS

  • Package Body Material:

    UNSPECIFIED

  • Package Code:

    HVQCCN

  • Package Equivalence Code:

    LCC32,.2SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE

  • Packing Method:

    TRAY

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    NO LEAD

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Width:

    5 mm

LCMXO2-1200ZE-1SG32C Frequently Asked Questions (FAQs)

  • Lattice provides a PCB layout and routing guide for the LCMXO2 family, which includes recommendations for signal integrity, power distribution, and thermal management. It's available on the Lattice website.
  • Lattice recommends using a daisy-chain configuration for JTAG, with each device connected in series. Make sure to follow the JTAG signal routing guidelines and use a JTAG cable with a 1.8V or 3.3V signal level.
  • The LCMXO2-1200ZE-1SG32C requires a specific power sequencing order: VCCIO, VCC, and then VCCAUX. The power supply voltage must be within the recommended range, and the power-on reset (POR) signal must be asserted during power-up.
  • Use the Lattice Power Calculator tool to estimate power consumption based on your design's specific requirements. Optimize power consumption by using low-power modes, reducing clock frequencies, and minimizing dynamic power consumption.
  • The LCMXO2-1200ZE-1SG32C has a maximum junction temperature of 100°C. Ensure good thermal conductivity by using a heat sink, thermal interface material, and a PCB with thermal vias. Monitor the device's temperature using the built-in thermal sensor.

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LCMXO2-1200ZE-1SG32C Overview

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Part Image LCMXO2-1200ZE-1SG32I Lattice Semiconductor Corporation

Field Programmable Gate Array, 87MHz, 1280-Cell