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LCMXO2-2000ZE-3MG132C - Lattice Semiconductor

Description: CPLD MachXO2 Family 1.2V 132-Pin CSBGA Tray

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PCB Footprints
LCMXO2-2000ZE-3MG132C - Lattice Semiconductor PCB footprint - BGA - BGA - 132-Ball csBGA
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3D Models
LCMXO2-2000ZE-3MG132C - Lattice Semiconductor  - 3D model - BGA - 132-Ball csBGA
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LCMXO2-2000ZE-3MG132C Details

  • Manufacturer Part Number:

    LCMXO2-2000ZE-3MG132C

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia, Philippines, Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    19

  • Clock Frequency-Max:

    86.6 MHz

  • JESD-30 Code:

    S-PBGA-B132

  • JESD-609 Code:

    e1

  • Length:

    8 mm

  • Moisture Sensitivity Level:

    3

  • Number of Inputs:

    104

  • Number of Logic Cells:

    2112

  • Number of Outputs:

    104

  • Number of Terminals:

    132

  • Operating Temperature-Max:

    85 °C

  • Organization:

    264 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFBGA

  • Package Equivalence Code:

    BGA132,14X14,20

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, LOW PROFILE, FINE PITCH

  • Packing Method:

    TRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.35 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    8 mm

LCMXO2-2000ZE-3MG132C Frequently Asked Questions (FAQs)

  • Lattice provides a PCB layout and routing guide for the LCMXO2 family, which includes recommendations for signal integrity, power distribution, and thermal management. It's available on the Lattice website.
  • Lattice recommends using a daisy-chain configuration for JTAG, with each device connected in series. Make sure to follow the JTAG signal routing guidelines and use a JTAG cable with a 1.8V or 3.3V signal level.
  • The LCMXO2-2000ZE-3MG132C requires a specific power sequencing order: VCCIO, VCC, and then VCCAUX. The power supply voltage must be within the recommended range, and the power-on reset (POR) signal must be asserted during power-up.
  • Lattice provides a Power Calculator tool that helps estimate power consumption based on the device's configuration, clock frequency, and other factors. You can also use the tool to optimize power consumption by selecting the most power-efficient features and settings for your design.
  • The LCMXO2-2000ZE-3MG132C has a maximum junction temperature of 100°C. To ensure reliable operation, you should provide adequate heat sinking, such as a heat sink or thermal pad, and follow Lattice's thermal management guidelines.

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LCMXO2-2000ZE-3MG132C Overview

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