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LCMXO2-640ZE-2TG100I - Lattice Semiconductor

Description: FPGA - Field Programmable Gate Array 640 LUTs 79 IO 1.2V 2 Spd

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PCB Footprints
LCMXO2-640ZE-2TG100I - Lattice Semiconductor PCB footprint - Quad Flat Packages - Quad Flat Packages - 100-Pin TQFP Package Option 1: MachXO2, MachXOTM, ispMACH® 4000
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3D Models
LCMXO2-640ZE-2TG100I - Lattice Semiconductor  - 3D model - Quad Flat Packages - 100-Pin TQFP Package Option 1: MachXO2, MachXOTM, ispMACH® 4000
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LCMXO2-640ZE-2TG100I Details

  • Manufacturer Part Number:

    LCMXO2-640ZE-2TG100I

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia, Philippines, Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    19

  • Clock Frequency-Max:

    93.1 MHz

  • JESD-30 Code:

    S-PQFP-G100

  • JESD-609 Code:

    e3

  • Length:

    14 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    80

  • Number of Inputs:

    78

  • Number of Logic Cells:

    640

  • Number of Outputs:

    78

  • Number of Terminals:

    100

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    80 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP100,.63SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Packing Method:

    TRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Width:

    14 mm

LCMXO2-640ZE-2TG100I Frequently Asked Questions (FAQs)

  • Lattice provides a PCB layout and routing guide for the LCMXO2 family, which includes recommendations for signal integrity, power distribution, and thermal management. It's available on the Lattice website.
  • Lattice recommends using a daisy-chain configuration for JTAG, with each device connected in series. Make sure to follow the JTAG signal routing guidelines and use a JTAG cable with a 1.8V or 3.3V signal level, depending on the device's I/O voltage.
  • The LCMXO2-640ZE-2TG100I requires a specific power sequencing order to ensure proper operation. The recommended sequence is: VCCIO, VCC, VCCAUX, and then VREF. Make sure to follow the power-up and power-down sequences carefully to avoid damage to the device.
  • Lattice provides a Power Calculator tool that helps estimate power consumption based on the device's configuration and usage. You can also use the Lattice Diamond software to optimize power consumption by selecting the optimal voltage and frequency for your design.
  • The LCMXO2-640ZE-2TG100I has a maximum junction temperature of 100°C. To ensure reliable operation, make sure to provide adequate heat sinking and airflow around the device. Lattice recommends using a thermal interface material and a heat sink with a thermal resistance of less than 10°C/W.

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LCMXO2-640ZE-2TG100I Overview

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Part Image LCMXO2-640ZE-2TG100C Lattice Semiconductor Corporation

Field Programmable Gate Array, 80 CLBS, 93.1MHz, 640-Cell, PQFP100