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LFE2-12E-5F256C - Lattice Semiconductor

Description: 12K LUTS, 193 I/O, DSP, 1.2V,

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LFE2-12E-5F256C - Lattice Semiconductor PCB footprint - BGA - BGA - 256-Ball ftBGA Package Option 2: LatticeECP3TM
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LFE2-12E-5F256C - Lattice Semiconductor  - 3D model - BGA - 256-Ball ftBGA Package Option 2: LatticeECP3TM
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LFE2-12E-5F256C Details

  • Manufacturer Part Number:

    LFE2-12E-5F256C

  • Pbfree Code:

    No

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    BGA

  • Package Description:

    FPBGA-256

  • Pin Count:

    256

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    311 MHz

  • Combinatorial Delay of a CLB-Max:

    0.358 ns

  • JESD-30 Code:

    S-PBGA-B256

  • JESD-609 Code:

    e0

  • Length:

    17 mm

  • Moisture Sensitivity Level:

    3

  • Number of Inputs:

    193

  • Number of Logic Cells:

    12000

  • Number of Outputs:

    193

  • Number of Terminals:

    256

  • Operating Temperature-Max:

    85 °C

  • Organization:

    1500 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA256,16X16,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    225

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Lead (Sn63Pb37)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    17 mm

LFE2-12E-5F256C Frequently Asked Questions (FAQs)

  • The LFE2-12E-5F256C FPGA has an industrial temperature range of -40°C to 100°C, making it suitable for a wide range of applications.
  • Lattice provides a Clock Domain Crossing (CDC) IP core that can be used to implement CDC in the LFE2-12E-5F256C FPGA. This IP core is available in the Lattice Diamond design software.
  • The power consumption of the LFE2-12E-5F256C FPGA depends on the specific application and usage. However, according to the datasheet, the typical static power consumption is around 100 mW, and the dynamic power consumption is around 200 mW at 100 MHz.
  • Yes, the LFE2-12E-5F256C FPGA has high-speed I/Os that support interfaces like PCIe and SATA. However, the specific implementation and performance will depend on the design and the requirements of the application.
  • Lattice provides a range of security features, including bitstream encryption, secure boot, and secure key storage, to help protect your design on the LFE2-12E-5F256C FPGA. These features can be implemented using the Lattice Diamond design software and the Lattice SecureControl helper IP core.

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LFE2-12E-5F256C Overview

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Part Image LFE2-12E-5F256I Lattice Semiconductor Corporation

Field Programmable Gate Array, 1500 CLBS, 311MHz, 12000-Cell, PBGA256