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LFEC20E-4FN484C - Lattice Semiconductor

Description: IC FPGA 360 I/O 484FBGA

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PCB Footprints
LFEC20E-4FN484C - Lattice Semiconductor PCB footprint - BGA - BGA - 484-Ball fpBGA
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3D Models
LFEC20E-4FN484C - Lattice Semiconductor  - 3D model - BGA - 484-Ball fpBGA
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LFEC20E-4FN484C Details

  • Manufacturer Part Number:

    LFEC20E-4FN484C

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    BGA

  • Pin Count:

    484

  • ECCN Code:

    3A991.D

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    420 MHz

  • Combinatorial Delay of a CLB-Max:

    0.48 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    2464

  • Number of Inputs:

    360

  • Number of Logic Cells:

    19700

  • Number of Outputs:

    360

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    85 °C

  • Organization:

    2464 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Width:

    23 mm

LFEC20E-4FN484C Frequently Asked Questions (FAQs)

  • Lattice provides a PCB layout guide and reference design files for the LFEC20E-4FN484C, which can be found on their website. It's recommended to follow these guidelines to ensure optimal signal integrity and minimize noise.
  • Lattice recommends using an external POR circuit with a voltage supervisor IC, such as the TLV7031, to ensure a reliable power-on reset. The POR circuit should be designed to meet the device's power-on reset timing requirements.
  • The device has a thermal junction-to-case rating of 2°C/W. To ensure reliable operation, it's recommended to use a heat sink or thermal pad, and to follow Lattice's thermal management guidelines for PCB design and layout.
  • Lattice provides a Clocking and PLL User Guide, which provides detailed information on configuring the device's clocking and PLL settings. Additionally, the Lattice Diamond software provides a Clocking Wizard tool to help with clocking configuration.
  • The recommended settings for the device's I/O banks and voltage levels depend on the specific application and interface requirements. Lattice provides a I/O Bank and Voltage Level User Guide, which provides detailed information on configuring the I/O banks and voltage levels.

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LFEC20E-4FN484C Overview

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Part Image LFEC20E-4FN484I Lattice Semiconductor Corporation

Field Programmable Gate Array, 2464 CLBs, 420MHz, 19700-Cell, PBGA484

Part Image LFEC20E-4F484I Lattice Semiconductor Corporation

Field Programmable Gate Array, 2464 CLBs, 420MHz, 19700-Cell, PBGA484