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LFXP2-30E-5FN484I - Lattice Semiconductor

Description: FPGA - Field Programmable Gate Array 30K LUTs 363 I/O Ins on DSP 1.2V -5 Spd

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LFXP2-30E-5FN484I - Lattice Semiconductor PCB footprint - BGA - BGA - 484-Ball fpBGA
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LFXP2-30E-5FN484I - Lattice Semiconductor  - 3D model - BGA - 484-Ball fpBGA
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LFXP2-30E-5FN484I Details

  • Manufacturer Part Number:

    LFXP2-30E-5FN484I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    BGA

  • Package Description:

    FBGA-484

  • Pin Count:

    484

  • Country Of Origin:

    Malaysia, Philippines, Taiwan

  • ECCN Code:

    3A991.D

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    9

  • Clock Frequency-Max:

    435 MHz

  • Combinatorial Delay of a CLB-Max:

    0.494 ns

  • JESD-30 Code:

    S-PBGA-B484

  • JESD-609 Code:

    e1

  • Length:

    23 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    3625

  • Number of Inputs:

    363

  • Number of Logic Cells:

    29000

  • Number of Outputs:

    363

  • Number of Terminals:

    484

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    3635 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA484,22X22,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    250

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    23 mm

LFXP2-30E-5FN484I Frequently Asked Questions (FAQs)

  • The LFXP2-30E-5FN484I has an operating temperature range of -40°C to 100°C.
  • Lattice recommends using a synchronizer or a FIFO to implement CDC in the LFXP2-30E-5FN484I. The specific implementation depends on the clock frequencies and the design requirements.
  • The power consumption of the LFXP2-30E-5FN484I depends on the device utilization, clock frequency, and voltage. According to the datasheet, the typical power consumption is around 1.2W at 1.2V and 50MHz.
  • Yes, the LFXP2-30E-5FN484I supports high-speed interfaces like PCIe and SATA. However, the specific implementation and performance may vary depending on the design and the interface requirements.
  • Lattice provides a DDR memory interface IP core for the LFXP2-30E-5FN484I. The IP core supports DDR2, DDR3, and DDR4 memory interfaces. The implementation requires a license and the IP core can be generated using the Lattice IPexpress tool.

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LFXP2-30E-5FN484I Overview

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Part Image LFXP2-30E-5FN484C Lattice Semiconductor Corporation

Field Programmable Gate Array, 3635 CLBS, 435MHz, 29000-Cell, CMOS, PBGA484

Part Image LFXP2-30E-5F484C Lattice Semiconductor Corporation

Field Programmable Gate Array, 3635 CLBS, 435MHz, 29000-Cell, CMOS, PBGA484

Part Image LFXP2-30E-5F484I Lattice Semiconductor Corporation

Field Programmable Gate Array, 3635 CLBS, 435MHz, 29000-Cell, CMOS, PBGA484