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NGTB40N135IHRWG - onsemi

Description: Obsolete - IGBT, 600V 40A Solar/UPS

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PCB Footprints
NGTB40N135IHRWG - onsemi PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - TO−247 CASE 340AL ISSUE D
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3D Models
NGTB40N135IHRWG - onsemi  - 3D model - Transistor Outline, Vertical - TO−247 CASE 340AL ISSUE D
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NGTB40N135IHRWG Details

  • Manufacturer Part Number:

    NGTB40N135IHRWG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TO-247

  • Pin Count:

    3

  • Manufacturer Package Code:

    340AL

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    4 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    0

  • Collector Current-Max (IC):

    80 A

  • Collector-Emitter Voltage-Max:

    1350 V

  • Gate-Emitter Thr Voltage-Max:

    6.5 V

  • Gate-Emitter Voltage-Max:

    20 V

  • JESD-609 Code:

    e3

  • Operating Temperature-Max:

    175 °C

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    394 W

  • Surface Mount:

    NO

  • Terminal Finish:

    MATTE TIN

NGTB40N135IHRWG Frequently Asked Questions (FAQs)

  • The maximum junction temperature for the NGTB40N135IHRWG is 150°C, as specified in the datasheet. However, it's recommended to operate the device at a lower temperature to ensure reliability and longevity.
  • To ensure proper biasing, follow the recommended operating conditions outlined in the datasheet, including the gate-source voltage (Vgs) and drain-source voltage (Vds) ranges. Additionally, ensure the device is operated within the recommended current and power dissipation limits.
  • Proper thermal management is crucial for the NGTB40N135IHRWG. Ensure good heat sinking, use a thermal interface material (TIM) if necessary, and follow the recommended PCB layout and thermal design guidelines to minimize thermal resistance and prevent overheating.
  • Yes, the NGTB40N135IHRWG is suitable for high-frequency switching applications due to its low gate charge and internal gate resistance. However, ensure the device is properly biased and the PCB layout is optimized for high-frequency operation to minimize parasitic inductance and capacitance.
  • To protect the NGTB40N135IHRWG from ESD, follow proper handling and storage procedures, use ESD-protective packaging and materials, and implement ESD protection circuits in your design, such as TVS diodes or ESD protection arrays.

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NGTB40N135IHRWG Overview

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