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NGTB40N60L2WG - onsemi

Description: Obsolete - IGBT, 650V 40A FS2 Induction Heating

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PCB Footprints
NGTB40N60L2WG - onsemi PCB footprint - Transistor Outline, Vertical - Transistor Outline, Vertical - TO−247 CASE 340AL ISSUE D
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3D Models
NGTB40N60L2WG - onsemi  - 3D model - Transistor Outline, Vertical - TO−247 CASE 340AL ISSUE D
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NGTB40N60L2WG Details

  • Manufacturer Part Number:

    NGTB40N60L2WG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TO-247-3

  • Manufacturer Package Code:

    340AL

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    2 Days

  • Manufacturer:

    onsemi

  • YTEOL:

    0

  • Collector Current-Max (IC):

    80 A

  • Collector-Emitter Voltage-Max:

    600 V

  • Gate-Emitter Thr Voltage-Max:

    6.5 V

  • Gate-Emitter Voltage-Max:

    20 V

  • JESD-609 Code:

    e3

  • Operating Temperature-Max:

    175 °C

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    417 W

  • Surface Mount:

    NO

  • Terminal Finish:

    MATTE TIN

NGTB40N60L2WG Frequently Asked Questions (FAQs)

  • The maximum safe operating area (SOA) for the NGTB40N60L2WG is not explicitly stated in the datasheet, but it can be estimated based on the device's thermal and electrical characteristics. A safe operating area can be determined by considering the device's maximum junction temperature, voltage, and current ratings.
  • To ensure proper thermal management, it's essential to provide a good thermal path from the device to a heat sink or the PCB. This can be achieved by using a thermal interface material (TIM) with a low thermal resistance, ensuring good contact between the device and the heat sink, and designing the PCB with thermal vias and a solid copper plane to dissipate heat.
  • The recommended gate drive voltage for the NGTB40N60L2WG is typically between 10V to 15V, depending on the specific application and switching frequency. A higher gate drive voltage can reduce switching losses, but it may also increase the risk of gate oxide damage.
  • To minimize EMI, it's essential to use proper PCB layout techniques, such as separating high-frequency and low-frequency circuits, using shielding, and minimizing loop areas. Additionally, using a snubber circuit or a gate drive with built-in EMI filtering can help reduce EMI emissions.
  • The maximum allowed dv/dt for the NGTB40N60L2WG is not explicitly stated in the datasheet, but it's typically in the range of 10V/ns to 50V/ns, depending on the specific application and operating conditions. Exceeding the maximum allowed dv/dt can lead to device failure or reduced reliability.

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NGTB40N60L2WG Overview

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