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NIS1161MTTAG - onsemi

Description: Low Capacitance (0.65 pF Typical, I/O to GND); Diode Capacitance Matching Between I/O’s: 1% Typical; Optimized Layout; Protection for the Following IEC Standards: IEC 61000−4−2 (Level 4); Low ESD Clamping Voltage; Short-to-Battery Blocking; These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant; NIV1161MTWTAG Wettable Flank Package; NIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

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PCB Footprints
NIS1161MTTAG - onsemi PCB footprint - Other - Other - WDFN6
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NIS1161MTTAG - onsemi  - 3D model - Other - WDFN6
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NIS1161MTTAG Details

  • Manufacturer Part Number:

    NIS1161MTTAG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    WDFN-6

  • Package Description:

    WDFN-6

  • Manufacturer Package Code:

    511CB

  • Country Of Origin:

    Malaysia

  • HTS Code:

    8542.39.00.01

  • Factory Lead Time:

    6 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    7

  • JESD-30 Code:

    S-PDSO-N6

  • JESD-609 Code:

    e3

  • Length:

    2 mm

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    6

  • Operating Temperature-Max:

    150 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    HVSON

  • Package Shape:

    SQUARE

  • Package Style:

    SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE

  • Peak Reflow Temperature (Cel):

    260

  • Seated Height-Max:

    0.8 mm

  • Surface Mount:

    YES

  • Telecom IC Type:

    GAS DISCHARGE TUBE SUPPRESSOR

  • Temperature Grade:

    MILITARY

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    NO LEAD

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    2 mm

NIS1161MTTAG Frequently Asked Questions (FAQs)

  • A 4-layer PCB with a solid ground plane and thermal vias is recommended. The device should be placed near a thermal pad or heat sink to dissipate heat efficiently.
  • Ensure proper thermal design, use a heat sink if necessary, and follow the recommended operating conditions. Also, consider using a thermal interface material to improve heat transfer.
  • The maximum allowed voltage on the input pins is 5.5V, which is the absolute maximum rating. Operating the device above this voltage can cause permanent damage.
  • Use ESD protection devices, such as TVS diodes or ESD arrays, on the input lines to protect the device from electrostatic discharge. Follow the recommended PCB layout and handling procedures to minimize ESD risks.
  • Power up the device in the following sequence: VCC, then VIN, and finally the input signals. This ensures proper device initialization and prevents latch-up or damage.

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