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NTTFD9D0N06HLTWG - onsemi

Description: Advance Package Technology in Small Footprint (3x3mm); Low RDS(on); Low Qg and Capacitance

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PCB Footprints
NTTFD9D0N06HLTWG - onsemi PCB footprint - Other - Other - WQFN12_CASE 510CJ
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NTTFD9D0N06HLTWG - onsemi  - 3D model - Other - WQFN12_CASE 510CJ
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NTTFD9D0N06HLTWG Details

  • Manufacturer Part Number:

    NTTFD9D0N06HLTWG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    WQFN-12

  • Package Description:

    WQFN-12

  • Manufacturer Package Code:

    510CJ

  • Country Of Origin:

    Philippines

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    13 Weeks

  • Date Of Intro:

    2020-02-19

  • Manufacturer:

    onsemi

  • YTEOL:

    5.6

  • Avalanche Energy Rating (Eas):

    46 mJ

  • Configuration:

    SERIES CONNECTED, 2 ELEMENTS WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    60 V

  • Drain Current-Max (ID):

    38 A

  • Drain-source On Resistance-Max:

    0.009 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    12.3 pF

  • JESD-30 Code:

    S-PQCC-N12

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    2

  • Number of Terminals:

    12

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    150 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    SQUARE

  • Package Style:

    CHIP CARRIER

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    26 W

  • Pulsed Drain Current-Max (IDM):

    349 A

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    NO LEAD

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

NTTFD9D0N06HLTWG Frequently Asked Questions (FAQs)

  • A recommended PCB layout for optimal thermal performance would be to use a minimum of 2 oz copper thickness, with a thermal relief pattern under the device, and a solid copper pour on the top and bottom layers. Additionally, it's recommended to use vias to connect the thermal pad to the thermal relief pattern.
  • To ensure the device is properly biased, it's essential to follow the recommended biasing scheme outlined in the datasheet. This includes setting the gate-source voltage (Vgs) to the recommended value, typically around 10-15V, and ensuring the drain-source voltage (Vds) is within the specified range. Additionally, it's crucial to provide a stable and low-impedance power supply to the device.
  • Critical thermal design considerations for the NTTFD9D0N06HLTWG include ensuring a low thermal resistance between the device and the heat sink, using a heat sink with a high thermal conductivity, and providing adequate airflow to dissipate heat. It's also essential to consider the thermal interface material (TIM) and its thermal conductivity, as well as the device's power dissipation and junction temperature.
  • To protect the NTTFD9D0N06HLTWG from ESD, it's recommended to follow standard ESD handling procedures, such as using an ESD wrist strap or mat, and ensuring that all equipment and tools are properly grounded. Additionally, it's essential to use ESD-sensitive devices and materials during assembly and handling, and to implement ESD protection circuits in the design.
  • Onsemi performs a range of reliability and qualification tests on the NTTFD9D0N06HLTWG, including high-temperature operating life (HTOL), high-temperature storage life (HTSL), temperature cycling, and electrostatic discharge (ESD) testing. These tests ensure the device meets the required standards for reliability and performance.

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