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NVMJS0D9N04CLTWG - onsemi

Description: Small Footprint; Low RdS(on); Low Qg and Capacitance; AEC-Q101 Qualified and PPAP Capable; RoHS Compliant

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NVMJS0D9N04CLTWG - onsemi PCB footprint - Other - Other - LFPAK8 4.90x4.80x1.12MM, 1.27P CASE 760AA ISSUE D
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NVMJS0D9N04CLTWG - onsemi  - 3D model - Other - LFPAK8 4.90x4.80x1.12MM, 1.27P CASE 760AA ISSUE D
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NVMJS0D9N04CLTWG Details

  • Manufacturer Part Number:

    NVMJS0D9N04CLTWG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Not Recommended

  • Part Package Code:

    LFPAK-8

  • Manufacturer Package Code:

    760AA

  • Country Of Origin:

    Mainland China, Malaysia, Philippines, Thailand, Vietnam

  • ECCN Code:

    EAR99

  • Date Of Intro:

    2018-12-04

  • Manufacturer:

    onsemi

  • YTEOL:

    3

  • Avalanche Energy Rating (Eas):

    706 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    40 V

  • Drain Current-Max (ID):

    330 A

  • Drain-source On Resistance-Max:

    0.0012 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    77 pF

  • JESD-30 Code:

    R-PDSO-X5

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    5

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    167 W

  • Pulsed Drain Current-Max (IDM):

    900 A

  • Reference Standard:

    AEC-Q101

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    UNSPECIFIED

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Element Material:

    SILICON

NVMJS0D9N04CLTWG Frequently Asked Questions (FAQs)

  • A good PCB layout for optimal thermal performance involves placing thermal vias under the package, using a solid ground plane, and keeping the thermal path as short as possible. It's also recommended to use a thermal pad on the bottom of the package.
  • To ensure reliable operation in high-temperature environments, it's essential to follow the recommended operating conditions, use a suitable thermal management system, and consider derating the device's performance. Additionally, ensure that the device is properly soldered and the PCB is designed to minimize thermal resistance.
  • To prevent damage, handle the device by the body, avoid touching the pins, and store it in an anti-static bag or wrap it in anti-static material. Avoid exposing the device to extreme temperatures, humidity, or physical stress.
  • To troubleshoot POR-related issues, check the power supply voltage, ensure that the voltage ramp-up is within the recommended specifications, and verify that the POR circuitry is not being triggered by noise or glitches. Also, review the device's datasheet and application notes for specific guidance.
  • The limited reprogrammability of the device means that the system design should consider the trade-offs between flexibility and cost. It may be necessary to implement additional logic or use a more programmable device to achieve the required level of flexibility.

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