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NVMYS4D1N06CLTWG - onsemi

Description: Small Footprint (5x6mm); Low RDS(on) ; Low QG and Capacitance; LFPAK4 Package; AEC−Q101 Qualified and PPAP Capable; These Devices are Pb−Free and are RoHS Compliant

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NVMYS4D1N06CLTWG Details

  • Manufacturer Part Number:

    NVMYS4D1N06CLTWG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    LFPAK-4

  • Manufacturer Package Code:

    760AB

  • Country Of Origin:

    Mainland China, Malaysia, Philippines, Thailand, Vietnam

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    15 Weeks

  • Date Of Intro:

    2018-12-11

  • Manufacturer:

    onsemi

  • YTEOL:

    6

  • Avalanche Energy Rating (Eas):

    185 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    60 V

  • Drain Current-Max (ID):

    22 A

  • Drain-source On Resistance-Max:

    0.0057 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JESD-30 Code:

    R-PSSO-G4

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    4

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    79 W

  • Pulsed Drain Current-Max (IDM):

    820 A

  • Reference Standard:

    AEC-Q101

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    GULL WING

  • Terminal Position:

    SINGLE

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Element Material:

    SILICON

NVMYS4D1N06CLTWG Frequently Asked Questions (FAQs)

  • The recommended PCB footprint for the NVMYS4D1N06CLTWG is a 5x6 pad layout with a 0.5mm pitch, as shown in the onsemi application note AND9173/D.
  • To ensure proper biasing, connect the gate to a voltage source through a 1kΩ resistor, and connect the source to ground through a 10Ω resistor. Also, ensure the drain is connected to a load or a voltage source.
  • The maximum allowed power dissipation for the NVMYS4D1N06CLTWG is 2.5W, as specified in the datasheet. Exceeding this limit may cause the device to overheat and fail.
  • Yes, the NVMYS4D1N06CLTWG is suitable for high-frequency switching applications up to 1MHz. However, ensure proper PCB layout and decoupling to minimize parasitic inductance and capacitance.
  • To protect the NVMYS4D1N06CLTWG from ESD, handle the device with an anti-static wrist strap or mat, and ensure the PCB has ESD protection diodes or resistors on the input and output pins.

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NVMYS4D1N06CLTWG Overview

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