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NVMYS7D3N04CLTWG - onsemi

Description: Small Footprint (5x6mm); Low RDS (ON); Low QG and Capacitance; LFPAK4 Package, Industry Standard; AEC−Q101 Qualified and PPAP Capable; These Devices are Pb−Free and are RoHS Compliant

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NVMYS7D3N04CLTWG Details

  • Manufacturer Part Number:

    NVMYS7D3N04CLTWG

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    LFPAK-4

  • Package Description:

    LFPAK-4

  • Manufacturer Package Code:

    760AB

  • Country Of Origin:

    Mainland China, Malaysia, Philippines, Thailand, Vietnam

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    14 Weeks

  • Manufacturer:

    onsemi

  • YTEOL:

    5

  • Avalanche Energy Rating (Eas):

    65 mJ

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    40 V

  • Drain Current-Max (ID):

    17 A

  • Drain-source On Resistance-Max:

    0.012 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JESD-30 Code:

    R-PSSO-G4

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    4

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    175 °C

  • Operating Temperature-Min:

    -55 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    38 W

  • Pulsed Drain Current-Max (IDM):

    269 A

  • Reference Standard:

    AEC-Q101

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    GULL WING

  • Terminal Position:

    SINGLE

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Element Material:

    SILICON

NVMYS7D3N04CLTWG Frequently Asked Questions (FAQs)

  • A 2-layer or 4-layer PCB with a solid ground plane and thermal vias is recommended. The device should be placed near a thermal pad or heat sink to dissipate heat efficiently.
  • Ensure that the device is operated within the recommended voltage and current ratings, and that the PCB is designed to minimize thermal resistance. Also, consider using thermal management techniques such as heat sinks or thermal interfaces.
  • Exceeding the maximum junction temperature can lead to reduced device lifespan, increased thermal resistance, and potentially catastrophic failure. It is essential to ensure that the device operates within the recommended temperature range.
  • Use ESD protection devices such as TVS diodes or ESD arrays on the input and output pins to protect against electrostatic discharge. Follow proper PCB design and handling practices to minimize ESD risks.
  • When operating multiple devices in parallel, ensure that each device has its own decoupling capacitor and that the PCB is designed to minimize inductive coupling between devices. Also, consider the total current rating and thermal management requirements.

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NVMYS7D3N04CLTWG Overview

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