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S29GL512T10DHI020 - Infineon

Description: FLASH - NOR Memory IC 512Mbit Parallel 100 ns 64-FBGA (9x9)

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S29GL512T10DHI020 - Infineon PCB footprint - BGA - BGA - LAE064_
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S29GL512T10DHI020 - Infineon  - 3D model - BGA - LAE064_
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S29GL512T10DHI020 Details

  • Manufacturer Part Number:

    S29GL512T10DHI020

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.32.00.51

  • Manufacturer:

    Infineon Technologies AG

  • YTEOL:

    10

  • Access Time-Max:

    100 ns

  • Alternate Memory Width:

    8

  • Boot Block:

    BOTTOM/TOP

  • JESD-30 Code:

    S-PBGA-B64

  • JESD-609 Code:

    e1

  • Length:

    9 mm

  • Memory Density:

    536870912 bit

  • Memory IC Type:

    FLASH

  • Memory Width:

    16

  • Moisture Sensitivity Level:

    3

  • Number of Functions:

    1

  • Number of Terminals:

    64

  • Number of Words:

    33554432 words

  • Number of Words Code:

    32000000

  • Operating Mode:

    ASYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    32MX16

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LBGA

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, LOW PROFILE

  • Parallel/Serial:

    PARALLEL

  • Peak Reflow Temperature (Cel):

    260

  • Programming Voltage:

    2.7 V

  • Seated Height-Max:

    1.4 mm

  • Supply Current-Max:

    0.06 mA

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    2.7 V

  • Supply Voltage-Nom (Vsup):

    3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Type:

    NOR TYPE

  • Width:

    9 mm

S29GL512T10DHI020 Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the S29GL512T10DHI020 is -40°C to +85°C.
  • The HOLD# signal should be asserted low to pause the current read or write operation, and de-asserted high to resume the operation.
  • The recommended power-up sequence is to apply VCC first, followed by VPP (if used), and then the clock signal (CLK).
  • The device density and configuration can be determined by reading the device ID and configuration registers, which can be accessed through the command interface.
  • The WP# signal is used to protect the device from accidental writes. When WP# is asserted low, the device is write-protected, and when it is de-asserted high, the device is write-enabled.

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S29GL512T10DHI020 Overview

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Part Image S29GL512T10DHI020 Cypress Semiconductor

Flash, 32MX16, 100ns, PBGA64