Part Image

SI7104DN-T1-GE3 - Vishay

Description: MOSFET 12V 35A 52W 3.7mohm @ 4.5V

Download SI7104DN-T1-GE3 Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
PCB Footprints
SI7104DN-T1-GE3 - Vishay PCB footprint - Other - Other - PowerPAK®  1212-8, (Single / Dual)
click to zoom
3D Models
SI7104DN-T1-GE3 - Vishay  - 3D model - Other - PowerPAK®  1212-8, (Single / Dual)
click to zoom

SI7104DN-T1-GE3 Details

  • Manufacturer Part Number:

    SI7104DN-T1-GE3

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Not Recommended

  • Package Description:

    HALOGEN FREE AND ROHS COMPLIANT, LEADLESS, 1212-8, POWERPAK-8

  • ECCN Code:

    EAR99

  • Factory Lead Time:

    15 Weeks

  • Manufacturer:

    Vishay Intertechnologies

  • YTEOL:

    3

  • Case Connection:

    DRAIN

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    12 V

  • Drain Current-Max (ID):

    26.1 A

  • Drain-source On Resistance-Max:

    0.0037 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JESD-30 Code:

    S-XDSO-C5

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    5

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    UNSPECIFIED

  • Package Shape:

    SQUARE

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    52 W

  • Pulsed Drain Current-Max (IDM):

    60 A

  • Qualification Status:

    Not Qualified

  • Surface Mount:

    YES

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    C BEND

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

SI7104DN-T1-GE3 Frequently Asked Questions (FAQs)

  • A good PCB layout for optimal thermal performance involves placing thermal vias under the package, using a solid ground plane, and keeping the thermal path as short as possible. A 4-layer PCB with a dedicated thermal layer is recommended.
  • To ensure reliable operation in high-temperature environments, ensure proper heat sinking, use a thermally conductive interface material, and follow the recommended derating guidelines for the device. Additionally, consider using a thermal interface material with a high thermal conductivity.
  • Exceeding the maximum junction temperature (Tj) rating can lead to reduced device lifespan, increased thermal resistance, and potentially catastrophic failure. It's essential to ensure that the device operates within the recommended temperature range to maintain reliability and performance.
  • To handle ESD protection, follow proper handling and storage procedures, use ESD-protective packaging, and implement ESD protection circuits in the design. The device has an internal ESD protection diode, but additional external protection may be necessary depending on the application.
  • When paralleling multiple devices, ensure that each device has its own heat sink, and the devices are matched for optimal performance. Additionally, consider the current sharing and thermal management implications, and ensure that the total current rating is not exceeded.

Trust Checks

This model has been provided by an expert contributor.
Expert Contribution
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored

SI7104DN-T1-GE3 Overview

Use the download button to access the SI7104DN-T1-GE3 schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like SI710, or try a keyword search, such as Power Field-Effect Transistors

Parts related to SI7104DN-T1-GE3

Showing 0 results