- Datasheet Download Datasheet
- Stock & Prices $ Price & Stock for SPP20N60C3
- Part Number SPP20N60C3
- Manufacturer Infineon
- Pin Count 3
- Part Category MOSFET (N-Channel)
- Package Category Transistor Outline, Vertical
- Footprint Name Transistor Outline, Vertical - PG-TO 220- FP
- Released Date Feb 25, 2020
- Last Modified Date Mar 7, 2023 4:10 PM UTC
- Pinout / Pin List Click Here (Member Only)
SPP20N60C3 Details
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Manufacturer Part Number:
SPP20N60C3
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Pbfree Code:
Yes
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Rohs Code:
Yes
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Part Life Cycle Code:
Not Recommended
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Part Package Code:
TO-220AB
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Pin Count:
3
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ECCN Code:
EAR99
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Manufacturer:
Infineon Technologies AG
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YTEOL:
3
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Additional Feature:
AVALANCHE RATED
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Avalanche Energy Rating (Eas):
690 mJ
SPP20N60C3 Frequently Asked Questions (FAQs)
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The maximum safe operating area (SOA) for the SPP20N60C3 is not explicitly stated in the datasheet. However, Infineon provides a SOA curve in the application note AN2013-01, which can be used to determine the maximum safe operating area for this device.
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To ensure the SPP20N60C3 is fully turned on, the gate-source voltage (Vgs) should be at least 10V, and the gate current should be sufficient to charge the gate capacitance quickly. A gate resistor value between 10Ω to 100Ω is recommended to limit the gate current and prevent oscillations.
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The maximum allowed drain-source voltage (Vds) for the SPP20N60C3 is 600V, as specified in the datasheet. However, it's essential to consider the maximum voltage rating, derating, and voltage spikes when designing the application.
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To handle thermal management for the SPP20N60C3, ensure good heat sinking, use a thermal interface material (TIM) with a thermal conductivity of at least 1 W/mK, and consider using a heat sink with a thermal resistance of less than 10°C/W. Monitor the junction temperature (Tj) and ensure it stays below the maximum rated temperature of 175°C.
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For the SPP20N60C3, a good PCB layout practice is to use a compact layout, minimize trace lengths, and use a ground plane to reduce electromagnetic interference (EMI). Keep the gate trace short and away from the drain trace to prevent oscillations. Use a Kelvin connection for the source pin to reduce parasitic inductance.
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SPP20N60C3 Overview
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