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TMPM369FDFG - Toshiba

Description: ARM Microcontrollers - MCU 32b ARM Cortex-M3 512kB ROM 128 RAM

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TMPM369FDFG - Toshiba PCB footprint - Quad Flat Packages - Quad Flat Packages - LQFP144-P-2020-0.50E
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TMPM369FDFG - Toshiba  - 3D model - Quad Flat Packages - LQFP144-P-2020-0.50E
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TMPM369FDFG Details

  • Manufacturer Part Number:

    TMPM369FDFG

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • HTS Code:

    8542.31.00.25

  • Factory Lead Time:

    24 Weeks

  • Manufacturer:

    Toshiba America Electronic Components

  • YTEOL:

    8

  • Has ADC:

    YES

  • Additional Feature:

    SUPPLY IS 3V-3.45V WHEN USB(2) IS USED, ALSO OPERATES AT 0-70DEGCEN EXCEPT DURING FLASH W/E

  • Address Bus Width:

    24

  • Bit Size:

    32

  • Boundary Scan:

    NO

  • Clock Frequency-Max:

    16 MHz

  • DAC Channels:

    YES

  • DMA Channels:

    YES

  • External Data Bus Width:

    16

  • JESD-30 Code:

    S-PQFP-G144

  • Length:

    20 mm

  • Number of I/O Lines:

    102

  • Number of Terminals:

    144

  • On Chip Program ROM Width:

    8

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • PWM Channels:

    YES

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    QFP

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK

  • RAM (bytes):

    131072

  • ROM (words):

    524288

  • ROM Programmability:

    FLASH

  • Speed:

    80 MHz

  • Supply Voltage-Max:

    3.6 V

  • Supply Voltage-Min:

    3.3 V

  • Supply Voltage-Nom:

    3.3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Width:

    20 mm

  • uPs/uCs/Peripheral ICs Type:

    MICROCONTROLLER, RISC

TMPM369FDFG Frequently Asked Questions (FAQs)

  • The recommended power-on sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures proper initialization of the internal voltage regulators and prevents latch-up.
  • The clock settings can be configured using the Clock Control Register (CCR). The CCR allows you to select the clock source, divide the clock frequency, and enable or disable the clock output.
  • The NMI pin is used to generate a non-maskable interrupt, which is a high-priority interrupt that cannot be masked by the CPU. It is typically used for critical events such as a watchdog timer timeout or a power failure.
  • The DMA controller can be used to transfer data between peripherals and memory without CPU intervention. The DMA controller is configured using the DMA Control Register (DMACR) and the DMA Transfer Register (DMATR).
  • The maximum operating frequency of the TMPM369FDFG is 160 MHz.

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TMPM369FDFG Overview

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