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W25Q80JVSNIQ - Winbond

Description: IC FLASH 8M SPI 133MHZ 8SOIC

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W25Q80JVSNIQ - Winbond PCB footprint - Small Outline Packages - Small Outline Packages - 8-Pin SOIC8 150-mil
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3D Models
W25Q80JVSNIQ - Winbond  - 3D model - Small Outline Packages - 8-Pin SOIC8 150-mil
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W25Q80JVSNIQ Details

  • Manufacturer Part Number:

    W25Q80JVSNIQ

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    SOIC-8

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.32.00.51

  • Manufacturer:

    Winbond Electronics Corp

  • YTEOL:

    0

  • Clock Frequency-Max (fCLK):

    133 MHz

  • JESD-30 Code:

    R-PDSO-G8

  • Length:

    4.85 mm

  • Memory Density:

    8388608 bit

  • Memory IC Type:

    FLASH

  • Memory Width:

    8

  • Number of Functions:

    1

  • Number of Terminals:

    8

  • Number of Words:

    1048576 words

  • Number of Words Code:

    1000000

  • Operating Mode:

    SYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    1MX8

  • Output Characteristics:

    3-STATE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Parallel/Serial:

    SERIAL

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Programming Voltage:

    3 V

  • Seated Height-Max:

    1.75 mm

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    2.7 V

  • Supply Voltage-Nom (Vsup):

    3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Type:

    NOR TYPE

  • Width:

    3.9 mm

W25Q80JVSNIQ Frequently Asked Questions (FAQs)

  • The W25Q80JVSNIQ has a minimum of 100,000 erase cycles, but the actual number of cycles may vary depending on usage and environmental conditions.
  • The HOLD# signal should be kept low during read and write operations. If the HOLD# signal is asserted high, the device will enter a 'hold' state, and all operations will be paused until the signal is de-asserted.
  • The recommended power-up sequence is to apply VCC first, followed by VPP (if used), and then the clock signal. This ensures proper device initialization and prevents latch-up conditions.
  • The WP# signal should be tied low to enable write operations. If WP# is tied high, the device will be in a write-protected state, and all write operations will be ignored.
  • The maximum operating frequency for the W25Q80JVSNIQ is 104 MHz, but the actual frequency may vary depending on the specific application and system design.

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W25Q80JVSNIQ Overview

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