WM8750CBLGEFL footprint, schematic symbol and 3D model by Cirrus Logic

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WM8750CBLGEFL Details

Manufacturer Part Number:
WM8750CBLGEFL
Rohs Code:
Yes
Part Life Cycle Code:
Obsolete
Package Description:
5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220VHHD-5, QFN-32
HTS Code:
8542.39.00.01
Manufacturer:
Cirrus Logic
YTEOL:
0
Filter:
YES
JESD-30 Code:
S-PQCC-N32
Length:
5 mm
Number of Functions:
1
Number of Terminals:
32
Operating Mode:
SYNCHRONOUS
Operating Temperature-Max:
85 °C
Operating Temperature-Min:
-25 °C
Package Body Material:
PLASTIC/EPOXY
Package Code:
HVQCCN
Package Shape:
SQUARE
Package Style:
CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Seated Height-Max:
1 mm
Supply Voltage-Nom:
1.5 V
Surface Mount:
YES
Technology:
CMOS
Telecom IC Type:
PCM CODEC
Temperature Grade:
OTHER
Terminal Form:
NO LEAD
Terminal Pitch:
0.5 mm
Terminal Position:
QUAD
Width:
5 mm

The recommended power-up sequence is to apply VDD first, followed by VDDIO, and then the clock signal. This ensures proper initialization of the device.
To configure the WM8750 for master clock mode, set the MCLK pin as an output by setting the MCLKOE bit in the Clock Control Register (CKCNTRL). Then, set the desired clock frequency using the MCLKDIV and MCLKFRQ registers.
The digital mute pin (DMUTE) is used to mute the digital audio output. When DMUTE is high, the digital audio output is muted, and when it's low, the output is enabled.
To optimize power consumption, use the Power Management Register (PWRCNTRL) to control the power-down modes of the device. Additionally, use the Dynamic Voltage and Frequency Scaling (DVFS) feature to adjust the clock frequency and voltage supply based on the system's requirements.
The maximum allowed capacitance for the WM8750's analog inputs is 10nF. Exceeding this value may affect the device's performance and stability.

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