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WM8805GEDS/V - Cirrus Logic

Description: Audio Transmitters, Receivers, Transceivers 8:1 Digi. Interface Transcvr with PLL

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WM8805GEDS/V - Cirrus Logic - PCB symbol
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PCB Footprints
WM8805GEDS/V - Cirrus Logic PCB footprint - Small Outline Packages - Small Outline Packages - 28 PIN SSOP
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3D Models
WM8805GEDS/V - Cirrus Logic - 3D model - Small Outline Packages - 28 PIN SSOP
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WM8805GEDS/V Details

  • Manufacturer Part Number:

    WM8805GEDS/V

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • HTS Code:

    8542.39.00.60

  • Factory Lead Time:

    111 Weeks

  • Manufacturer:

    Cirrus Logic

  • YTEOL:

    0

  • Consumer IC Type:

    CONSUMER CIRCUIT

  • JESD-30 Code:

    R-PDSO-G28

  • Length:

    10.2 mm

  • Number of Functions:

    1

  • Number of Terminals:

    28

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SSOP

  • Package Equivalence Code:

    SSOP28,.3

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, SHRINK PITCH

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2 mm

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    2.7 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Width:

    5.3 mm

WM8805GEDS/V Frequently Asked Questions (FAQs)

  • A 4-layer PCB with a solid ground plane and a separate power plane is recommended. Keep the analog and digital sections separate, and use a star-configuration for the power supply. Refer to the Cirrus Logic application note AN215 for more details.
  • To configure the WM8805GEDS/V for Master Clock Mode, set the MCLK pin to the desired clock frequency, and set the MCLKDIV pin to the appropriate division ratio. Ensure that the clock source is stable and meets the specified jitter requirements.
  • The recommended power-up sequence is: 1) Power up the analog supply (AVDD), 2) Power up the digital supply (DVDD), and 3) Apply the clock signal. Ensure that the power supplies are stable before applying the clock signal.
  • Use a logic analyzer to verify the I2S clock and data signals. Check the I2S configuration registers to ensure that the correct format and sample rate are set. Verify that the I2S clock is stable and within the specified frequency range.
  • The maximum cable length supported by the WM8805GEDS/V's S/PDIF interface is approximately 10 meters (33 feet) using a high-quality, shielded coaxial cable.

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