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XC95144XL-7CS144I - AMD

Description: CPLD - Complex Programmable Logic Devices 3.3V 144-mc CPLD

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PCB Footprints
XC95144XL-7CS144I - AMD PCB footprint - BGA - BGA - CS144
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XC95144XL-7CS144I - AMD  - 3D model - BGA - CS144
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XC95144XL-7CS144I Details

  • Manufacturer Part Number:

    XC95144XL-7CS144I

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    CSP-144

  • HTS Code:

    8542.31.00.55

  • Factory Lead Time:

    111 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    0

  • Additional Feature:

    YES

  • Clock Frequency-Max:

    138.88 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PBGA-B144

  • JESD-609 Code:

    e0

  • JTAG BST:

    YES

  • Length:

    12 mm

  • Moisture Sensitivity Level:

    3

  • Number of I/O Lines:

    117

  • Number of Inputs:

    117

  • Number of Macro Cells:

    144

  • Number of Outputs:

    117

  • Number of Terminals:

    144

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    0 DEDICATED INPUTS, 117 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TFBGA

  • Package Equivalence Code:

    BGA144,13X13,32

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    240

  • Programmable Logic Type:

    FLASH PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max:

    3.6 V

  • Supply Voltage-Min:

    3 V

  • Supply Voltage-Nom:

    3.3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    TIN LEAD

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    12 mm

XC95144XL-7CS144I Frequently Asked Questions (FAQs)

  • The maximum operating frequency of XC95144XL-7CS144I is 180 MHz.
  • To implement a CDC in XC95144XL-7CS144I, you can use a synchronizer circuit or a FIFO-based CDC. The synchronizer circuit uses two or more flip-flops to synchronize the data, while the FIFO-based CDC uses a FIFO to buffer the data and a clock domain crossing circuit to synchronize the read and write clocks.
  • The power consumption of XC95144XL-7CS144I depends on the operating frequency, voltage, and temperature. According to the datasheet, the typical power consumption is around 1.5W at 180 MHz, 3.3V, and 25°C.
  • To implement a reset in XC95144XL-7CS144I, you can use the dedicated reset pin (RST) or use a logic-based reset circuit. The dedicated reset pin is asynchronous and can be used to reset the device, while the logic-based reset circuit can be used to reset specific modules or blocks.
  • The maximum I/O bandwidth of XC95144XL-7CS144I is around 1.8 GB/s, assuming a 180 MHz clock frequency and 32-bit data bus.

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XC95144XL-7CS144I Overview

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