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XC9536XL-7VQ44I - AMD

Description: CPLD - Complex Programmable Logic Devices 3.3V 36-mc CPLD

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XC9536XL-7VQ44I - AMD PCB footprint - Quad Flat Packages - Quad Flat Packages - VQFP (VQ44/VQG44)
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XC9536XL-7VQ44I - AMD  - 3D model - Quad Flat Packages - VQFP (VQ44/VQG44)
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XC9536XL-7VQ44I Details

  • Manufacturer Part Number:

    XC9536XL-7VQ44I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    VQFP-44

  • HTS Code:

    8542.31.00.55

  • Factory Lead Time:

    111 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    0

  • Additional Feature:

    YES

  • Clock Frequency-Max:

    138.88 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PQFP-G44

  • JESD-609 Code:

    e4

  • JTAG BST:

    YES

  • Length:

    10 mm

  • Moisture Sensitivity Level:

    3

  • Number of I/O Lines:

    34

  • Number of Inputs:

    34

  • Number of Macro Cells:

    36

  • Number of Outputs:

    34

  • Number of Terminals:

    44

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    0 DEDICATED INPUTS, 34 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TQFP

  • Package Equivalence Code:

    TQFP44,.47SQ,32

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, THIN PROFILE

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FLASH PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max:

    3.6 V

  • Supply Voltage-Min:

    3 V

  • Supply Voltage-Nom:

    3.3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Nickel/Palladium/Gold (Ni/Pd/Au)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    10 mm

XC9536XL-7VQ44I Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VCCINT before VCCO, and to ensure that VCCINT reaches its minimum specified voltage before applying a clock signal or toggling any input.
  • During power-up, the JTAG interface should be in a high-impedance state until VCCINT reaches its minimum specified voltage. During power-down, the JTAG interface should be driven to a known state to prevent unwanted device behavior.
  • The maximum allowable voltage on the I/O pins during power-up and power-down is VCCO + 0.5V to prevent damage to the device.
  • The device can be configured using the JTAG interface or the Master Reset (MR) pin. The MR pin should be asserted low during power-up to ensure that the device is properly configured.
  • The recommended clock frequency during power-up and power-down is 0 Hz to prevent unwanted device behavior.

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XC9536XL-7VQ44I Overview

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