Part Image

XCZU19EG-2FFVC1760E - AMD

Description: Zynq® UltraScale+™ MPSoCs

Download XCZU19EG-2FFVC1760E Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
PCB Footprints
XCZU19EG-2FFVC1760E - AMD PCB footprint - BGA - BGA - FVC1760
click to zoom
3D Models
XCZU19EG-2FFVC1760E - AMD  - 3D model - BGA - FVC1760
click to zoom

XCZU19EG-2FFVC1760E Details

  • Manufacturer Part Number:

    XCZU19EG-2FFVC1760E

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Package Description:

    FCBGA-1760

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.30

  • Factory Lead Time:

    16 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    19

  • JESD-30 Code:

    S-PBGA-B1760

  • JESD-609 Code:

    e1

  • Length:

    42.5 mm

  • Moisture Sensitivity Level:

    4

  • Number of Terminals:

    1760

  • Operating Temperature-Max:

    100 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Seated Height-Max:

    3.71 mm

  • Supply Voltage-Max:

    0.876 V

  • Supply Voltage-Min:

    0.825 V

  • Supply Voltage-Nom:

    0.85 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    42.5 mm

  • uPs/uCs/Peripheral ICs Type:

    SoC

XCZU19EG-2FFVC1760E Frequently Asked Questions (FAQs)

  • The recommended PCB layout and stackup for the XCZU19EG-2FFVC1760E can be found in the Xilinx PCB Design Guide (UG583) and the Zynq UltraScale+ FPGA PCB Design and Pin Planning Guide (UG583). These guides provide detailed information on PCB layout, layer stackup, and signal routing to ensure optimal signal integrity.
  • To optimize power consumption and thermal management, refer to the Xilinx Power Estimation and Optimization Guide (UG786) and the Zynq UltraScale+ FPGA Power Management Guide (UG584). These guides provide guidance on power estimation, optimization techniques, and thermal management strategies for the XCZU19EG-2FFVC1760E.
  • The recommended clocking and reset strategies for the XCZU19EG-2FFVC1760E can be found in the Xilinx Clocking Wizard Guide (UG472) and the Zynq UltraScale+ FPGA Clocking and Reset Guide (UG585). These guides provide detailed information on clocking architectures, clock domain crossing, and reset strategies to ensure reliable and efficient system operation.
  • To ensure signal integrity and reduce EMI, refer to the Xilinx Signal Integrity Guide (UG582) and the Zynq UltraScale+ FPGA PCB Design and Pin Planning Guide (UG583). These guides provide guidance on signal integrity, EMI reduction, and PCB design best practices for the XCZU19EG-2FFVC1760E.
  • The recommended design flows and tools for developing and verifying designs for the XCZU19EG-2FFVC1760E can be found in the Xilinx Vivado Design Suite User Guide (UG912) and the Zynq UltraScale+ FPGA Development Guide (UG586). These guides provide detailed information on design flows, tool usage, and verification strategies for the XCZU19EG-2FFVC1760E.

Trust Checks

This model has been provided by community users.
Community Provided
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored

XCZU19EG-2FFVC1760E Overview

Use the download button to access the XCZU19EG-2FFVC1760E schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like XCZU1, or try a keyword search, such as Other uPs/uCs/Peripheral ICs

Parts related to XCZU19EG-2FFVC1760E

Showing 0 results