Flash Memories||Other Memory ICs||SRAMs Footprint, Symbol and 3D Model search results

Showing 25 of 867810 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V3557S80PFGI Renesas Electronics	1	The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control signal registers. The outputs are flow-through (no output data register).	Quad Flat Packages	71V3557S80PFGI	3D model available Symbol and footprint available 3	1 Download Model
	70T3399S133BFI8 Renesas Electronics	1	The 70T3399 is a high-speed 128K x 18 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3399 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3399S133BFI8	3D model available Symbol and footprint available 3	1 Download Model
	5962-3829413MZA Renesas Electronics	1	The 5962-38294 (7164 SRAM) is organized as 8K x 8 and offers a reduced power standby mode. The low-power version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation.	Ceramic Dual-In-Line Packages	5962-3829413MZA	3D model not available Symbol and footprint available 2	1 Download Model
	RMQC4A1818DGBA-302#AC0 Renesas Electronics	1	The RMQC4A1836DGBA is a 524, 288-word by 36-bit and the RMQC4A1818DGBA is a 1, 048, 576-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed	BGA	RMQC4A1818DGBA-302#AC0	3D model available Symbol and footprint available 3	1 Download Model

	71V416L10BEG8 Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L10BEG8	3D model available Symbol and footprint available 3	1 Download Model
	RMQCHA3636DGBA-222#AC0 Renesas Electronics	1	The RMQCHA3636DGBA is a 1, 048, 576-word by 36-bit and the RMQCHA3618DGBA is a 2, 097, 152-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Sp	BGA	RMQCHA3636DGBA-222#AC0	3D model available Symbol and footprint available 3	1 Download Model
	70T3799MS133BBGI Renesas Electronics	1	The 70T3799M is a high-speed 128K x 72 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3799M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3799MS133BBGI	3D model available Symbol and footprint available 3	1 Download Model
	70T633S10BC Renesas Electronics	1	The 70T633 is a high-speed 512K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.	BGA	70T633S10BC	3D model available Symbol and footprint available 3	1 Download Model
	R1LV5256ESA-5SI#S1 Renesas Electronics	1	The R1LV5256E Series is a family of low voltage 256-Kbit static RAMs organized as 32, 768-word by 8-bit, fabricated by Renesas’s high-performance 0. 15um CMOS and TFT technologies. The R1LV5256E Series has realized higher density, higher performance and low power consumption. The R1LV5256E Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. It has been packaged in 28-pin SOP and 28-pin TSOP.	Other	R1LV5256ESA-5SI#S1	3D model not available Symbol and footprint available 2	1 Download Model
	71V35761SA200BQG8 Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	BGA	71V35761SA200BQG8	3D model available Symbol and footprint available 3	1 Download Model
	71V35761SA166BGGI Renesas Electronics	1	The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.	BGA	71V35761SA166BGGI	3D model available Symbol and footprint available 3	1 Download Model
	70V631S12BF8 Renesas Electronics	1	The 70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/ SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each po	BGA	70V631S12BF8	3D model available Symbol and footprint available 3	1 Download Model
	7133LA90GB Renesas Electronics	1	The 7133 high-speed 2K x 16 Dual-Port Static RAMs is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the 7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200μW for a 2V battery. Military grade product in compliance with MIL-PRF-38535 QML is available.	Other	7133LA90GB	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S75BQ8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67703S75BQ8	3D model available Symbol and footprint available 3	1 Download Model
	5962-8855204UA Renesas Electronics	1	The 5962-88552 (71256 SRAM) is organized as 32K x 8. This part offers a reduced power standby mode for significant system level power and cooling savings. It also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Ceramic Dual-In-Line Packages	5962-8855204UA	3D model not available Symbol and footprint available 2	1 Download Model

	71421LA20PFG Renesas Electronics	1	The 71421 is a high-speed 2K x 8 Dual-Port Static RAM with internal interrupt logic for interprocessor communications. It is designed to be used as a "SLAVE" Dual-Port RAM together with the 71321 "MASTER" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode.	Quad Flat Packages	71421LA20PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S100PFGI Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65803S100PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V546S100PFGI Renesas Electronics	1	The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V546 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V546S100PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V3556S100PFG8 Renesas Electronics	1	The 71V3556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3556 contains data I/O, address and control signal registers.	Quad Flat Packages	71V3556S100PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S150BG Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S150BG	3D model available Symbol and footprint available 3	1 Download Model
	5962-8700208ZA Renesas Electronics	1	The 5962-87002 (IDT 7132/42) is a high-speed 2K x 8 Dual-Port Static RAM designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with a "SLAVE" Dual-Port in 16-bit-or-more word width systems which would result in full-speed, error free operation without the need for additional discrete logic. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with M	Ceramic Dual-In-Line Packages	5962-8700208ZA	3D model not available Symbol and footprint available 2	1 Download Model
	71V546S100PFGI8 Renesas Electronics	1	The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V546 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V546S100PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V416L12BE8 Renesas Electronics	1	The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	BGA	71V416L12BE8	3D model available Symbol and footprint available 3	1 Download Model
	70T3589S133BCI8 Renesas Electronics	1	The 70T3589 is a high-speed 64K x 36 bit synchronous Dual-Port RAM that has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3589 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.	BGA	70T3589S133BCI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S150PFGI8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65803S150PFGI8	3D model available Symbol and footprint available 3	1 Download Model
23 24 25 26 27 28 29 30 31

Can't find what you're looking for? Request this part

Flash Memories||Other Memory ICs||SRAMs Model Download Search Results

Popular SRAMs