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Image	Part Number	D.S	Description	Prices / Stock	Model	Action
	72V2113L7-5PF8 Renesas Electronics	1	The 72V2113 512K x 9/256K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2113L7-5PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2103L10PFI8 Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2103L10PFI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2111L10PF8 Renesas Electronics	1	The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Super	72V2111L10PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2103L7-5PF8 Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2103L7-5PF8	3D model not available Symbol and footprint not available 0	0 Build or Request

	72V2111L15PFI8 Renesas Electronics	1	The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Super	72V2111L15PFI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2101L15PF Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	72V2101L15PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V211L15J Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	72V211L15J	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V211L15PF8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	72V211L15PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2111L15PF Renesas Electronics	1	The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Super	72V2111L15PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2101L15PFI8 Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	72V2101L15PFI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V211L10J8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	72V211L10J8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2101L10PF Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	72V2101L10PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2101L20PF8 Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	72V2101L20PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2103L6PF8 Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2103L6PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2103L10PF Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2103L10PF	3D model not available Symbol and footprint not available 0	0 Build or Request

	72V2105L15PF Renesas Electronics	1	The 72V2105 is an 256K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	72V2105L15PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2111L20PF Renesas Electronics	1	The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Super	72V2111L20PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2101L20PF Renesas Electronics	1	The 72V2101 is a 256K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this Supe	72V2101L20PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2103L15PF Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2103L15PF	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2113L10PFI8 Renesas Electronics	1	The 72V2113 512K x 9/256K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2113L10PFI8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2105L20PF8 Renesas Electronics	1	The 72V2105 is an 256K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	72V2105L20PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V211L15JI Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	72V211L15JI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2103L10PFI Renesas Electronics	1	The 72V2103 256K x 9/128K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	72V2103L10PFI	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V211L20PF8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	72V211L20PF8	3D model not available Symbol and footprint not available 0	0 Build or Request
	72V2105L20PF Renesas Electronics	1	The 72V2105 is an 256K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	72V2105L20PF	3D model not available Symbol and footprint not available 0	0 Build or Request
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