2305 Footprint, Symbol and 3D Model search results

Showing 25 of 89512 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	2305A-1HDCG Renesas Electronics	1	The 2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305A is an 8-pin version of the 2309A. The 2305A accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-c	Small Outline Packages	2305A-1HDCG	3D model available Symbol and footprint available 3	1 Download Model
	2305390-1 TE Connectivity	1	Wire-to-Board, Horizontal, 10 Position, Board Mount, A Code, 1.8 mm [.071 in] Centerline, Signal, Data Connectivity Headers	Other	2305390-1	3D model available Symbol and footprint available 3	1 Download Model
	2305-H-RC Bourns	1	Toroid power inductor 22uH horizontal Bourns 22 μH ±15% Leaded Inductor, 16.4A Idc, 7mΩ Rdc 2300	Other	2305-H-RC	3D model available Symbol and footprint available 3	1 Download Model
	2305-V-RC Bourns	1	Fixed Inductors 22uH 15% Vertical	Other	2305-V-RC	3D model available Symbol and footprint available 3	1 Download Model

	2305987-1 TE Connectivity	1	Body Features: Primary Product Color Black \| Connector & Keying Code A \| Configuration Features: PCB Mount Orientation Horizontal \| Number of Sections 2 \| Number of Positions 4 \| Number of Rows 1 \| Contact Features: Mating Tab Width .019 INCH \| Mating Tab Width .5 MM \| Contact Type Tab \| Mating Tab Thickness .016 INCH \| Contact Size .5mm \| Mating Tab Thickness .4 MM \| Contact Current Rating (Max) 3 AMP \| Contact Mating Area Plating Material Tin \| Housing Features: Centerline (Pitch) 7.8 MM \| Centerline (Pit	Other	2305987-1	3D model available Symbol and footprint available 3	1 Download Model
	2305908-2 TE Connectivity	1	Body Features: Primary Product Color Black \| Product Orientation Right Angle \| Configuration Features: Stacking Configuration Side Stackable \| Number of Positions 2 \| Number of Rows 1 \| Contact Features: Contact Base Material Copper Alloy \| Contact Current Rating (Max) 15 AMP \| Contact Mating Area Plating Material Tin \| Electrical Characteristics: Operating Voltage 300 VAC \| Housing Features: Centerline (Pitch) .197 INCH \| Housing Material Thermoplastic \| Centerline (Pitch) 5 MM \| Mechanical Attachment: Con	Other	2305908-2	3D model available Symbol and footprint available 3	1 Download Model
	2305908-4 TE Connectivity	1	Body Features: Primary Product Color Black \| Product Orientation Right Angle \| Configuration Features: Number of Rows 1 \| Number of Positions 4 \| Stacking Configuration Side Stackable \| Contact Features: Contact Base Material Copper Alloy \| Contact Mating Area Plating Material Tin \| Contact Current Rating (Max) 15 AMP \| Electrical Characteristics: Operating Voltage 300 VAC \| Housing Features: Centerline (Pitch) .197 INCH \| Centerline (Pitch) 5 MM \| Housing Material Thermoplastic \| Mechanical Attachment: Con	Other	2305908-4	3D model available Symbol and footprint available 3	1 Download Model
	2305A-1DCGI Renesas Electronics	1	The 2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305A is an 8-pin version of the 2309A. The 2305A accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-c	Small Outline Packages	2305A-1DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1DCGI8 Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1DCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1DCGI Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1HDCGI8 Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1PGGI Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1PGGI	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1PGG Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1PGG	3D model available Symbol and footprint available 3	1 Download Model
	2305A-1DCG8 Renesas Electronics	1	The 2305A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305A is an 8-pin version of the 2309A. The 2305A accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-c	Small Outline Packages	2305A-1DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2305B-1PGGI8 Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1PGGI8	3D model available Symbol and footprint available 3	1 Download Model

	2305B-1HDCGI Renesas Electronics	1	The 2305B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2305B is an 8-pin version of the 2309B. The 2305B accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-	Small Outline Packages	2305B-1HDCGI	3D model available Symbol and footprint available 3	1 Download Model
	2305908-8 TE Connectivity	1	Body Features: Primary Product Color Black \| Product Orientation Right Angle \| Configuration Features: Number of Positions 8 \| Number of Rows 1 \| Stacking Configuration Side Stackable \| Contact Features: Contact Current Rating (Max) 15 AMP \| Contact Mating Area Plating Material Tin \| Contact Base Material Copper Alloy \| Electrical Characteristics: Operating Voltage 300 VAC \| Housing Features: Housing Material Thermoplastic \| Centerline (Pitch) 5 MM \| Centerline (Pitch) .197 INCH \| Operation/Application: Cir	Other	2305908-8	3D model available Symbol and footprint available 3	1 Download Model
	2305-1HDCG8 Renesas Electronics	1	The 2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The 2305 is available in two different versions. The 2	Small Outline Packages	2305-1HDCG8	3D model available Symbol and footprint available 3	1 Download Model
	2305-1HDCGI Renesas Electronics	1	The 2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The 2305 is available in two different versions. The 2	Small Outline Packages	2305-1HDCGI	3D model available Symbol and footprint available 3	1 Download Model
	2305-1HDCG Renesas Electronics	1	The 2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The 2305 is available in two different versions. The 2	Small Outline Packages	2305-1HDCG	3D model available Symbol and footprint available 3	1 Download Model
	2305-1HDCGI8 Renesas Electronics	1	The 2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The 2305 is available in two different versions. The 2	Small Outline Packages	2305-1HDCGI8	3D model available Symbol and footprint available 3	1 Download Model
	2305-1DCGI Renesas Electronics	1	The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The IDT2305 is available in two different version	Small Outline Packages	2305-1DCGI	3D model available Symbol and footprint available 3	1 Download Model
	2305-1DCG8 Renesas Electronics	1	The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The IDT2305 is available in two different version	Small Outline Packages	2305-1DCG8	3D model available Symbol and footprint available 3	1 Download Model
	2305-1DCG Renesas Electronics	1	The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The IDT2305 is available in two different version	Small Outline Packages	2305-1DCG	3D model available Symbol and footprint available 3	1 Download Model
	2305-1DCGI8 Renesas Electronics	1	The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The IDT2305 is available in two different version	Small Outline Packages	2305-1DCGI8	3D model available Symbol and footprint available 3	1 Download Model
1 2 3 4 5 6 7 8 9

Can't find what you're looking for? Request this part

2305 Model Download Search Results

Popular Clock Drivers