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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V2556S150PFG8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S150PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S150PFG Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2546S150PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V25761S183PFG8 Renesas Electronics	1	The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V25761S183PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S133BGI8 Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S133BGI8	3D model available Symbol and footprint available 3	1 Download Model

	71V2556SA100BGG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGG	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S166PFG8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S166PFG8	3D model available Symbol and footprint available 3	1 Download Model
	71V25761S200PFGI Renesas Electronics	1	The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V25761S200PFGI	3D model available Symbol and footprint available 3	1 Download Model
	71V25761S183PFGI8 Renesas Electronics	1	The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V25761S183PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V25761S200PFGI8 Renesas Electronics	1	The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36 and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V25761S200PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA133BGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA133BGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA166BG8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA166BG8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S150PFG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S150PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BGGI Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BGGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S166PFG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S166PFG	3D model available Symbol and footprint available 3	1 Download Model

	71V2556S133PFG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S133PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S100PFG Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S100PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S100BGI Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S100BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S100PFGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S100PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556SA100BGG8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2556SA100BGG8	3D model available Symbol and footprint available 3	1 Download Model
	71V2546S133BGI Renesas Electronics	1	The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V2546S133BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S166PFGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S166PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S133PFGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S133PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S150PFGI8 Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S150PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V2556S166PFGI Renesas Electronics	1	The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V2556S166PFGI	3D model available Symbol and footprint available 3	1 Download Model
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