A15P- Footprint, Symbol and 3D Model search results

Showing 25 of 37231 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	KF22X-A15P-N Kycon	1	D-Sub Standard Connectors .318 15P PLUG R/A BRD LOCK	Other	KF22X-A15P-N	3D model not available Symbol and footprint available 2	1 Download Model
	71V256SA15PZGI8 Renesas Electronics	1	The 71V256SA 3.3V CMOS Asynchronous SRAM is organized as 32K x 8. When in standby mode, its very low power characteristics contribute to extended battery life. Under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to be less than 6.6mW. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Other	71V256SA15PZGI8	3D model available Symbol and footprint available 3	1 Download Model
	72261LA15PF8 Renesas Electronics	1	The 72261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSyn	Quad Flat Packages	72261LA15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72255LA15PFI8 Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA15PFI8	3D model available Symbol and footprint available 3	1 Download Model

	71V016SA15PHGI8 Renesas Electronics	1	The 71V016 3.3V CMOS SRAM is organized as 64K x 16. All bidirectional inputs and outputs of the 71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Small Outline Packages	71V016SA15PHGI8	3D model available Symbol and footprint available 3	1 Download Model
	72271LA15PFI8 Renesas Electronics	1	The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperS	Quad Flat Packages	72271LA15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	L717SDA15POL2 Amphenol Communications Solutions	1	Dsub, Stamped Signal 3A, Straight PCB Thru Hole, Back Insulator Plus Back Shell Height 6.0mm, 15 Pin, Flash Gold, Bright Tin Shell+Grounding Dimples, 3.05mm (.120in) Clear Hole, Without Standoff&Boardlock	Other	L717SDA15POL2	3D model available Symbol and footprint available 3	1 Download Model
	72271LA15PF Renesas Electronics	1	The 72271 is a 32K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperS	Quad Flat Packages	72271LA15PF	3D model available Symbol and footprint available 3	1 Download Model
	72265LA15PFGI Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	7201LA15P Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7201LA15P	3D model available Symbol and footprint available 3	1 Download Model
	71256SA15PZG8 Renesas Electronics	1	The 71256SA 5V CMOS SRAM is organized as 32K x 8. All bidirectional inputs and outputs of the 71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71256SA15PZG8	3D model available Symbol and footprint available 3	1 Download Model
	V100ZA15P LITTELFUSE	1	100 V 4.5 kA Varistor 1 Circuit Through Hole Disc 14mm,-55°C ~ 85°C	Other	V100ZA15P	3D model available Symbol and footprint available 3	1 Download Model
	MB8265A-15P Ramxeed	1	65,536-BIT Dynamic Random Access memory	Dual-In-Line Packages	MB8265A-15P	3D model available Symbol and footprint available 3	1 Download Model
	IXTA15P15T LITTELFUSE	1	P-Channel MOSFET -150V -15A	Other	IXTA15P15T	3D model available Symbol and footprint available 3	1 Download Model
	71V124SA15PHG Renesas Electronics	1	The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.	Small Outline Packages	71V124SA15PHG	3D model available Symbol and footprint available 3	1 Download Model

	7202LA15P Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7202LA15P	3D model available Symbol and footprint available 3	1 Download Model
	72265LA15PFI8 Renesas Electronics	1	The 72265 is a 16K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data	Quad Flat Packages	72265LA15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	7202LA15PDGI Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Ceramic Dual-In-Line Packages	7202LA15PDGI	3D model not available Symbol and footprint available 2	1 Download Model
	71256SA15PZGI8 Renesas Electronics	1	The 71256SA 5V CMOS SRAM is organized as 32K x 8. All bidirectional inputs and outputs of the 71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation.	Other	71256SA15PZGI8	3D model available Symbol and footprint available 3	1 Download Model
	7201LA15PI Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7201LA15PI	3D model available Symbol and footprint available 3	1 Download Model
	7202LA15PI Renesas Electronics	1	The 7202 is a 1K x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Dual-In-Line Packages	7202LA15PI	3D model available Symbol and footprint available 3	1 Download Model
	72V265LA15PFGI8 Renesas Electronics	1	The 72V265 is an 16K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72265 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V265LA15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	DF13A-15P-1.25H(21) Hirose	1	Hirose DF13 Series, 1.25mm Pitch 15 Way 1 Row Right Angle PCB Header, Solder Termination, 1A	Other	DF13A-15P-1.25H(21)	3D model not available Symbol and footprint available 2	1 Download Model
	DF14A-15P-1.25H(26) Hirose	1	Headers & Wire Housings 15P SNG ROW PIN HDR R/A SMT	Other	DF14A-15P-1.25H(26)	3D model available Symbol and footprint available 3	1 Download Model
	AS7C164A-15PIN Alliance Memory	1	SRAM - Asynchronous Memory IC 64Kbit Parallel 15 ns 28-PDIP	Dual-In-Line Packages	AS7C164A-15PIN	3D model available Symbol and footprint available 3	1 Download Model
1 2 3 4 5 6 7 8 9

Can't find what you're looking for? Request this part

A15P- Model Download Search Results

Popular D Type Connectors